• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.573-577
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• 2007

터치 센서를 이용한 휴대단말용 인터페이스가 다양하게 개발되면서 차세대 인터랙션 수단으로서 많은 주목을 받고 있지만, 버튼 인터페이스에 비해 오동작에 취약하고 터치 인터페이스만의 차별성을 확보하지 못하고 있는 실정이다. 본 논문에서는 터치 드래그 동작을 주요 인터랙션 수단으로 활용한 모바일 기기용 사용자 인터페이스를 개발하여 오동작을 최소화하고 사용자가 조작할 때 즐거움을 줄 수 있는 UI 요소로 활용할 수 있도록 하였다. 본 논문에서 개발한 터치 인터페이스는 기기의 내부/외부 방향의 스크롤 동작을 각각 drag-in/drag-out 동작으로 칭하고 이러한 드래그 동작을 응용 프로그램의 실행과 종료에 할당하였으며 터치 센서를 따라 움직이는 스크를 동작은 기존과 동일하게 일반적인 스크롤 행위를 지시하는데 적용하였다. 제안한 인터랙션 방법은 터치 센서의 형태에 따라 크게 두 가지 방식으로 구현하였다. 첫 번째 방법은 기기 스크린 외곽에 터치 센서를 이열(二列) 배치하여, 터치스크린을 사용하지 않고도 스크린 주변의 터치 센서를 활용한 drag-in/out 동작의 감지가 가능하도록 하였다. 두 번째 구현 방법은 정전용량형 터치 센서 IC를 활용해 터치 스크린 기능과 함께 스크린 주변의 기기 케이스의 일부까지도 사용자의 접촉을 감지할 수 있도록 하였다. 기존 저항 방식 터치 스크린과 달리 본 논문에서 활용한 방식은 스크린과 케이스에서 동시에 터치를 감지할 수 있으며, 다접점 감지 알고리즘의 개발로 두 개의 손가락을 이용한 다양한 터치 인터랙션으로 활용할 수 있다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.565-566
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• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Journal of IKEEE
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• v.14 no.3
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• pp.250-255
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• 2010

The interleaved power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. The buck-boost converter used to provide the high output voltage and low output voltage for portable applications. Also we used the PWM(Pulse Width Modulation) control method for high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The interleaved PMIC to reduce output ripple. And step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.91-100
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• 2004

In this paper, we propose the method that analyzes the depth of object using 2 images in the disparity algorithm. It also presents the design and implementation of the proposed method for a real time processing. The proposed system uses the vertical strip structure for calculating similar pixel numbers for the processing and converts the depth of object into gray scale images in order to be displayed on various display devices. The hardware using the proposed method is operating with 30 frames/sec and verified by using the Altera APEX 20K1000EBC652-3. The proposed method is also Implemented into It by using the Hynix 0.35${\mu}{\textrm}{m}$ CB35 ASIC library and 256PQFP package.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.48-54
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• 2004

We have developed a new experimental driving system in order to make an easier drive experiment of PDP. By using the system, we can design and simulate the timing of the pulse in computer environment. As a result of the designed timing, we are able to program at PLD(Programmable Logic Device) and control high-voltage FET switches. The new system can reduce the time of the pulse compared with the previous logic gate ICs that realizes switching logic through hardware. In addition, it is a much easier way of changing the timing of the pulse due to the change of the driving method. By using the developed driving system we experimented on two different things- First, the realization of ADS Driving Method that run commonly; Second, gray scale realization on the three electrodes AC PDP.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.6
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• pp.58-63
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• 2006

FIB equipment can perform sputtering and chemical vapor deposition simultaneously. It is very advantageously used to fabricate a micro structure part having 3D shape because the minimum beam size of ${\Phi}10nm$ and smaller is available. Since general FIB uses very short wavelength and extremely high energy, it can directly make a micro structure less than $1{\mu}m$. As a result, FIB has been probability in manufacturing high performance micro devices and high precision micro structures. Until now, FIB has been commonly used as a very powerful tool in the semiconductor industry. It is mainly used for mask repair, device correction, failure analysis, IC error correction, etc. In this paper FIB-Sputtering and FIB-CVD characteristic analysis were carried out according to $Ga^+$ ion beam current that is very important parameter for minimizing the pattern size and maximizing the yield. Also, for FIB-Sputtering burr caused by redeposition of the substrate characteristic analysis was carried out.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.481-482
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• 2006

Chemical-mechanical polishing, the dominant technology for LSI planarization, is trending to play an important function in micro-electro mechanical systems (MEMS). However, MEMS CMP process has a couple of different characteristics in comparison to LSI device CMP since the feature size of MEMS is bigger than that of LSI devices. Preliminary CMP tests are performed to understand material removal rate (MRR) with blanket wafer under a couple of polishing pressure and velocity. Based on the blanket CMP data, this paper focuses on the consumable approach to enhance MEMS CMP by the adjustment of slurry and pad. As a mechanical tool, newly developed microstructured (MS) pad is applied to compare with conventional pad (IC 1400-k Nitta-Haas), which is fabricated by micro melding method of polyurethane. To understand the CMP characteristics in real time, in-situ friction force monitoring system was used. Finally, the topography change of poly-si MEMS structures is compared according to the pattern density, size and shape as polishing time goes on.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• Korean Journal of Optics and Photonics
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• v.22 no.1
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• pp.35-39
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• 2011

The PSPICE equivalent circuit elements of a 1550 nm InGaAsP laser diode were derived by using multi-level rate equations. The device parameters were extracted by using a self-consistent numerical method for the optical gain properties of the MQW active regions. The resulting equivalent circuit model is also applied to an actual optical transmitter, and its PSPICE simulation results show good agreement with the measured results once the parasitic capacitance due to the packaging is taken into account.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.139-144
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• 2016

This paper describes functional circuits of DC-DC converter IC incorporated with variable frequency PFM technique. In case of output voltage of DC-DC converter is reached setting value or output current is low then PFM switching frequency is slow down. In this work a PFM signal generator, a PFM Frequency Control Circuit, an output voltage detector and an over current protection circuits are designed. This device has been designed at a $0.35[{\mu}m]$, double poly, double metal 12[V] CMOS process.