• Laser Solutions
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• v.14 no.1
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• pp.14-18
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• 2011

Semiconductor industry demands decrease in line/space dimensions of IC substrates. Particularly for IC substrates for CPU, line/space dimensions below $10{\mu}m/10{\mu}m$ are expected to be used in production since 2014. Conventional production technologies (SAP, etc.) based on photolithography are widely agreed to be reaching capability limits. To address this limitation, the embedded circuit fabrication technology using laser ablation has been recently developed. In this paper, we used a nanosecond UV laser and a picosecond UV laser to fabricate embedded circuit patterns into a buildup film with $SiO_2$ powders for IC substrate. We conducted SEM and EDS analysis to investigate surface quality of the embedded circuit patterns. Experimental results showed that due to higher recoil pressure, picosecond UV laser ablation of the buildup film generated a better surface roughness.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.133-136
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• 2001

A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1049-1052
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• 1998

A new simplified circuit model for the switching noise analysis of the complicated multi-layer IC package is developed. The current flowing mechanism on the ground and power planes of the package is simplified by using the dependent current soures and partial plane circuit model. The methodology is very cost-efficient as well as accurate. It is demonstrated that the nosie based on the simplified circuit model has an excellent agreement with that of the complicated full circuit model. However, the simplified model takes only 5 minutes for the switching noise simulation, while the full circuit model takes more than 4 hours.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.75-80
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• 2004

By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.2
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• pp.357-362
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• 2020

The TMFT, a sub-system of TINC, provides voice calls, data transmission and reception, and multimedia services to individual users. At the time of development in 2011, the power circuit of the TMFT was designed to electrical power supply to each device via a charger IC. However, the newly improved power supply circuit allows power to be supplied to each device through the PMIC without configuring the charger IC separately. In this paper, the power circuit design structure of TMFT applied in the development stage and the improved power circuit design structure were compared. And we verified through experiments whether the improved power circuit can be applied to TMFT. The experimental method was verified by directly comparing the current consumption test, charge time comparison test, and rising temperature test during charging each of before and after improvement terminals.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.4
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• pp.14-21
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• 2012

This paper study a method of modeling and simulation of LED driver circuit for a design optimization. Simplified LED modeling is introduced and a driver IC, HV9910, is modeled by implementing the major function blocks. Circuit of buck type converter is constructed for simulation. Simulation includes not only the internal function of IC but also the various performance results such as LED array current control and dimming. Experiment results are also shown to prove the verification of its usage. This results show that the simulation approach is valid for a circuit optimization and a reduction of development time.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.937-940
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• 2000

This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.4
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• pp.612-616
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• 2012

This paper presents an active current regulator for LED driver IC. The proposed driver circuit is consists of DC-DC converter for supplying constant DC voltage to LED, active current regulator for compensating channel-to-channel current error from LED strings and feedback circuit for controlling duty ratio of the converter. The proposed active current regulator senses current of LED channels by equalizing both $V_{DS}$ and $V_{GS}$ at LED current control transistor. Because the proposed circuit directly measures the LED channel current without a sensing resistor and regulates all channel with same regulation loop, the power consumption and the current error are much small compared with previous works. The measured maximum efficiency of overall LED driver IC is approximately 94% and current error of LED channel-to-channel is under ${\pm}1.3%$. The proposed LED driver IC is fabricated Dongbu 0.35um BCD process.