• Journal of Internet Computing and Services
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• v.8 no.2
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• pp.67-76
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• 2007

Data used for the SFP module are stored in A0 and A2 memory area based on the SFP-MSA standard. In this paper the auto set-up program for SFP module has been designed and implemented. In order to make the Digital Diagnostic Monitoring Interface, the specific value has been written into the designated register via RS232 communication channel in the LD Driver IC. The Agilent VEE is used as a programming language for factory automation, and optical characteristics of SFP module and SFP-MSA standard are main structure of the implementation. The implemented program has been applied to the manufacturing field and the system gains a higher effect than the result of 6-Sigma.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.120-126
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• 1989

IC chip layout pattern recognition algorithms using image processing techniques are being developed for the automation of manufacturing and inspecting chips. Recognitioin of chip pattern requires feature extraction from nach rrame of chip image adn needs to match the feature data through all frames. In this paper, vertex position and form having layout information are extracted by the feature straightening algorithm, and global coordinates of layout pattern are extracted by the feature straightening algorithm, and global coordinates of layout pattern are obtainnd by vertex form matching from the overlapped area of neighbour frame.

• Journal of the Korean Society of Safety
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• v.28 no.3
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• pp.51-55
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• 2013

The purpose of this study is to find the causes of malfunctions and defective operation of printed circuit boards(PCBs) built into home refrigerators to perform power saving functions. This study performed an electrostatic test of a PCB built-in using an Auto Triggering system; lightning and impulse tests using an LSS-15AX; and an impulse test using an INS-400AX. From the analysis of a secondarily developed product, it was found that electrostatic discharge(ESD) caused more malfunctions and defective operations than electric overstress(EOS) due to overvoltage. As a result of increasing the condenser capacity of the PCB circuit, withstanding voltage was increased to 7.4 kV. In addition, this study changed the power saving mode and connected a varistor to the #2 pin of an IC chip. As a result, the system consisting of all specimens of a finally developed product was operated stably with an applied voltage of less than 10 kV. This study found it necessary to perform quality control at the manufacturing stage in order to reduce the occurrence of electrostatic accidents to IC chips built into a PCB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.716-722
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• 2017

In this paper, a fully printed NFC tag operating at 13.56 MHz was designed and fabricated using silver nano-paste and carbon ink. The proposed NFC tag has a printed coil with an inductance of $2.74{\mu}H$ on a PI film for application to an NFC tag IC with an internal capacitance of 50 pF. Screen printing technology used in this paper has advantages such as large area printing for mass production, low cost and eco-friendly process compared to conventional PCB manufacturing process. The proposed structure consists of a circular coil implemented as a single layer using silver nano-paste and carbon ink, a jumper pattern for chip mounting between the outer edge and the center of the coil, and an insulation pattern between the coil and the jumper pattern. In order to verify the performance of the proposed NFC tag, we performed the measurements of the printing line width, thickness, line resistance, adhesion and environmental reliability, and confirmed the suitability of the NFC tag based on the full-printed manufacturing method.

• Journal of the Korean Society of Food Science and Nutrition
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• v.46 no.5
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• pp.639-645
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• 2017

Differences in bioactive compounds and antioxidant activities of aronia leaf (AL) extracts according to manufacturing conditions such as different number of pan-roasting and different temperatures were investigated. Both total polyphenolic compounds and total flavonoids contents were the highest in six time-pan-roasted AL tea extract ($37.96{\pm}0.48mg$ catechin equivalent/g and $19.96{\pm}0.44mg$ quercetin equivalent/g, respectively) among four tea samples. Antioxidative activities were also the highest in six time-pan-roasted AL tea extract with $IC_{50}$ 0.43 mg/mL and $IC_{50}$ 0.27 mg/mL based on DPPH and ABTS radical scavenging activities, respectively. HPLC analysis revealed that AL tea infusion did not have caffeine regardless of manufacturing conditions, whereas green tea infusion had 3.8 mg/g caffeine. Results demonstrated that AL tea can be expected as caffeine free leaf tea containing antioxidant benefits. Moreover, specific pan-roasting conditions of AL tea would be very important for its functional and sensory attributes.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.3
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• pp.230-236
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• 2016

This research attempted simplifications to the LED street light for price competitiveness. The street light was simplified by replacing the SMPS with an IC driver on the PCB using an AC-type LED. The optical element that shape of a line-shaped lens covered LED crowded. Thus, this study aims to improve LED efficiency by using the minimum optical system. In order to satisfy the M3 regulation of street lighting at grade, the lens was divided into two parts depending on the forward direction of the light. Further, the changes in the number of LEDs located on part 1 and part 2 of the lens were analyzed. Through simulation, we determined the proper light distribution that meets M3 regulation of street lighting.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.6
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• pp.58-63
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• 2006

FIB equipment can perform sputtering and chemical vapor deposition simultaneously. It is very advantageously used to fabricate a micro structure part having 3D shape because the minimum beam size of ${\Phi}10nm$ and smaller is available. Since general FIB uses very short wavelength and extremely high energy, it can directly make a micro structure less than $1{\mu}m$. As a result, FIB has been probability in manufacturing high performance micro devices and high precision micro structures. Until now, FIB has been commonly used as a very powerful tool in the semiconductor industry. It is mainly used for mask repair, device correction, failure analysis, IC error correction, etc. In this paper FIB-Sputtering and FIB-CVD characteristic analysis were carried out according to $Ga^+$ ion beam current that is very important parameter for minimizing the pattern size and maximizing the yield. Also, for FIB-Sputtering burr caused by redeposition of the substrate characteristic analysis was carried out.

• Journal of the Korea Safety Management & Science
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• v.6 no.4
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• pp.155-170
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• 2004

Among the semiconductor If-chips, unlike memory chips, a majority of Application Specific IC(ASIC) products are produced by customer orders, and meeting the customer specified due date is a critical issue for the case. However, to the one who understands the nature of semiconductor manufacturing, it does not take much effort to realize the difficulty of meeting the given specific production due dates. Due to its multi-layered feature of products, to be completed, a semiconductor product(called device) enters into the fabrication manufacturing process(FAB) repeatedly as many times as the number of the product specified layers, and fabrication processes of individual layers are composed with similar but not identical unit processes. The unit process called photo-lithography is the only process where every layer must pass through. This re-entrant feature of FAB makes predicting and planning of due date of an ordered batch of devices difficult. Parallel machines problem in the photo process, which is bottleneck process, is solved with restricted roll out algorithm. Roll out algorithm is a method of solving the problem by embedding it within a dynamic programming framework. Restricted roll out algorithm Is roll out algorithm that restricted alternative states to decrease the solving time and improve the result. Results of simulation test in condition as same as real FAB facilities show the effectiveness of the developed algorithm.

• IE interfaces
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• v.25 no.2
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• pp.264-275
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• 2012

The process of semiconductor(IC Package) manufacturing usually includes lots of complex and sequential processes. Many kinds of equipments are installed with the mixed concept of serial and parallel manufacturing system. The business environments of the semiconductor industry have been changed frequently, because new technologies are developed continuously. It is the main reason of new investment plan and layout consideration. However, it is difficult to change the layout after installation, because the major equipments are expensive and difficult to move. Furthermore, it is usually a multiple-objective problem. Thus, new investment or layout change should be carefully considered when the production environments likewise product mix and production quantity are changed. This paper introduces a simulation case study of a Korean company that produces packaging substrates(especially lead frames) and requires multi-objective decision support. $QUEST^{(R)}$ is used for simulation modelling and AHP(Analytic Hierarchy Process) and DEA(Data Envelopment Analysis) are used for weighting of qualitative performance measures and solving multiple-objective layout problem, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.29-33
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• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.