• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1990.10a
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• pp.55-59
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10$\mu\textrm{m}$) were fabricated using RTP(Rapid Thermal Processor) and hydrogen passivation. The N+ Source, drain and gate were annealed and recrystallized using RTP at temperature of 1000$^{\circ}C$-1100$^{\circ}C$. But the active areas were now specially crystallized before growing the gate oxide. Without the hydrogen passivation, excellent transistor characteristics (ON/OFF=5${\times}$10$\^$6/, s=85mv/dec, I$\_$L/=51pA/$\mu\textrm{m}$) were obtained for 1.5$\mu\textrm{m}$ MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.34-45
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• 1994

We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.268-270
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• 2002

For analysis of semiconductor's electrons transmission characteristics, Impact ionization(I.I.) is very important. I.I. are generation process of electron-hole pairs. Therefore, the characteristics of device can change along with applied voltage or temperature. In this paper, we are scaled down the gate length to 50nm. Also, using TCAD simulator, we are analyzed I.I. and breakdown about three models-Van Overstraeten , Okuto and Ours models.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.53-63
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• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• Journal of Information Display
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• v.2 no.3
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• pp.66-71
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• 2001

MCFEDs (MOSFET-Contoolled Field Emission Displays) were fabricated to evaluate the validity of MCFEA for display application. The electrical properties of FEAs (Field Emitter Arrays), HVMOSFETs (High-Voltage MOSFETs), and MCFEAs (MOSFET-Controlled Field Emitter Arrays) were measured. The extraction gate voltage of the FEAs to obtain the anode current of 10 nA/tip was around 71 V. The breakdown voltages of the HVMOSFETs were above 81 V for all the samples. The I-V characteristics of the MCFEAs showed that the emission currents of the FEAs were well controlled depending on the control gate voltages of the HVMOSFETs. To avoid the harmful effects during the packaging process, the performance of the MCFEDs was evaluated in a high vacuum chamber. The emission images of the MCFEDs were controlled through very-through operation. From the comparison with a conventional FED, it was proven that the poor uniformity of FED could be improved through the integration with HVMOSFET.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.9
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.6-11
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different GPNS(Gate to Primary $N^+$ Diffusion Space) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device with FPW(Full P-Well) structure and non-CPS(Counter Pocket Source) implant shows typical SCR-like characteristics with low on-resistance(Ron), low snapback holding voltage(Vh) and low thermal breakdown voltage(Vtb), which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW(Partial P-Well) structure and optimal CPS implant demonstrate the improved ESD protection performance as a function of GPNS variation. GPNS was a important parameter, which is satisfied design window of ESD protection device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.207-209
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• 2004

Currently, for satisfying the needs of scaled MOSFET's a high quality thin oxide dielectric is desired because the properties of conventional $SiO_2$ film are not acceptable for these very small sized transistors. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over conventional $SiO_2$, to obtain the superior characteristics of ultra thin dielectric films, $N_2O$ grown thin oxynitride has been proposed as a dielectric growtuanneal ambient. In this study the authors observed process characteristics of $N_2O$ grown thin dielectric. In view points of the process characteristics of MOS capacitor, the sheet resistance of 4.07$[\Omega/sq.]$, the film stress of $1.009e^{10}[dyne/cm^2]$, the threshold voltage$(V_t)$ of 0.39[V], the breakdown voltage(BV[V]) of 11.45[V] was measured in PMOS. I could achieve improved electrical characteristics and reliability for deep submicron MOSFET devices with $N_2O$ thin oxide.