• Journal of Information Technology Applications and Management
• /
• v.11 no.2
• /
• pp.179-190
• /
• 2004

This paper describes the design of hacking prevention systems using a smart card. It consists of two parts, i.e., PC authentication and Keyboard-buffer hacking prevention. PC authentication function is a procedure to handle the access control to the target PC. The card's serial number is used for PIN(Personal Identification Number) and is converted into hash-code by SHA-1 hash-function to verify the valid users. The Keyboard-buffer hacking prevention function converts the scan codes into the encoded forms using RSA algorithm on the Java Card, and puts them into the keyboard-buffer to protect from illegal hacking. The encoded information in the buffer is again decoded by the RSA algorithm and displayed on the screen. in this paper, we use RSA_PKCS#1 algorithm for encoding and decoding. The reason using RSA technique instead of DES or Triple-DES is for the expansion to multi-functions in the future on PKI. Moreover, in the ubiquitous computing environment, this smart card security system can be used to protect the private information from the illegal attack in any computing device anywhere. Therefore, our security system can protect PC user's information more efficiently and guarantee a legal PC access authority against any illegal attack in a very convenient way.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.794-798
• /
• 1992

We present an optical Voltage and current sensor using $BSO(Bi_{12}SiO_{20})$ monocrystal. The voltage and current sensor consist of PBS(Polarizing Beam Splitter), 1/4 wavelength plate, ZnSe, Selfoc lens, LED, and PIN-PD etc. Magnetic core was made using permalloy for applying magnetic field to current sensor effectively. Current was measured from 100 to 1,600 ampere and accuracy was about ${\pm}$5%. The accuracy could be improved to ${\pm}$l% after reducing the nonlinear property of BSO crystal using our own program in PC (IBM286). We noticed that these data were not influenced by 154,000 voltage at all. Applied voltage was reduced to 1/20 using capacitors. And experiment was carried out up to 450V of the reduced voltage. The data fran optical voltage sensor was similar to that from conventional voltage sensor. The accuracy of the data was within about ${\pm}$1%.

• Investigative Magnetic Resonance Imaging
• /
• v.1 no.1
• /
• pp.75-78
• /
• 1997

A dual birdcage RF coil is proposed for MRI and MRA of the human leg. The proposed coil c can be used to cover the whole human leg by imaging upper and lower parts of the leg separately. In the conventional leg imaging scheme using a single RF coil, the leg has to be r relocated when changing the position of the RF coil thus causing problems in matching the i images from two sets of coils. When using the proposed dual RF coil, however, only the bed h has to be moved to select the imaging region while only one part of the dual coil is used each t time by using current switching and PIN diodes. The utility of proposed coil has been verified b by volunteer MRI and MRA and the imaging results show that the coil is useful for the clinical MRI and MRA of the leg.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.186-194
• /
• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.7 s.337
• /
• pp.1-4
• /
• 2005

A four-channel photoreceiver ways have been realized in a 0.8$\mu$m Si/SiGe HBT technology for the applications of parallel optical interconnects. The receiver array includes four-channel transimpedance amplifiers (TIAs) and p-i-n photodiodes, where the TIAs exploit a common-emitter (CE) input configuration. Measured results demonstrate that the four-channel CE TIA array provides 3.9GHz bandwidth, 62dB$\Omega$ transimpedance gain, 7.5pA/sqrt(Hz) average noise current spectral density, and less than -25dB crosstalk between adjacent channels with 40mW power dissipation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.995-998
• /
• 2003

This paper presents the deposition of poly-Si thin-film and fabrication of a solar cell by VHF-PECVD method. The poly-Si thin films. and pin-type solar cells are fabricated using multi-chamber cluster tool system. A 7.4% conversion efficiency was achieved from poly-Si thin film solar cells with total thickness less than $5{\mu}m$. The physical characteristic was measured by Raman spectroscopy, solar cell characteristic was measured under AM1.5 illumination.

• Journal of Korean Association for Spatial Structures
• /
• v.4 no.2 s.12
• /
• pp.81-88
• /
• 2004

The dynamic instability of snapping phenomena has been studied by many researchers. Few papers deal with dynamic buckling under loads with periodic characteristics, and the behavior under periodic excitations is expected to be different from behavior under STEP excitations. We investigate the fundamental mechanisms of the dynamic instability when the sinusoidally shaped arch structures are subjected to sinusoidally distributed excitations with pin-ends. The mechanisms of dynamic indirect snapping of shallow arches are especially investigated under not only STEP function excitations but also under sinusoidal harmonic excitations, applied i the up-and-down direction. The dynamic nonlinear responses are obtained by the numerical integration of the geometrically nonlinear equation of motion. And using this analyze characteristics of the dynamic instability through the running response spectrum by FFT(Fast Fourier Transform).

• ETRI Journal
• /
• v.29 no.4
• /
• pp.421-429
• /
• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.16 no.5
• /
• pp.151-156
• /
• 2007

In this paper, the creep characteristics of lead and lead-free solder joint were investigated using the QFP(Quad Flat Package) creep test. Two kind of solder pastes(Sn-3Ag-0.5Cu, Sn-0.2Sb-0.4Ag-37.4Pb) were applied to the QFP solder joints and each specimen was checked the external and internal failures(i.e., wetting failure, void, pin hole, poor-heel fillet) by digital microscope and X-ray inspection. The creep test was conducted at the temperatures of $100^{\circ}C$ and $130^{\circ}C$ under the load of 15$\sim$20% of average pull strength in solder joints. The creep characteristics of each solder joints were compared using the creep strain-time curve and creep strain rate-stress curves. Through the comparison, the Sn-3Ag-0.5Cu solder joints have higher creep resistance than that of Sn-0.3Sb-0.4Ag-37.4Pb. Also, the grain boundary sliding in the fracture surface and the necking of solder joint were observed by FE-SEM.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.5
• /
• pp.34-42
• /
• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.