• Title/Summary/Keyword: I/O module

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A Study on 8- Axis Servo Sync Control method and Implementation Using PLC Position Control Module (PLC에 의한 8축 동기제어의 구현)

  • Kim, S.W.;Kim, J.S.;Ryou, J.S.;Lee, Y.J.
    • Proceedings of the KIEE Conference
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    • 1995.07b
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    • pp.880-882
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    • 1995
  • The systematic function of the PLC (Programmable - Logic Controller) has been enhanced immensely due to the various special modules that consist of the conventional I/O control contants plus special function, which enables the flexible application to highly advanced systems. Position control module is one of the various PLC special module. In this paper, we proposed new synchronized operating method and implemented 8 - axis servo control system. The validity of proposed method is verified througth experimental results and it will be possible to expand 32 - axis servo control system by RS - 485 communication spec.

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A Study on Reliability Improvement of a Fault Tolerant Digital Governor (내고장성 디지털 조속기의 신뢰성 향상에 관한 연구)

  • Sin, Myeong-Cheol;Jeon, Il-Yeong;Jo, Seong-Hun;Lee, Seong-Geun;Kim, Yun-Sik
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.51 no.5
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    • pp.175-181
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    • 2002
  • In this paper, fault tolerant digital governor is designed to realize ceaseless controlling and to improve the reliability of control system. Designed digital governor huts duplex I/O module and triplex CPU module and also 2 out of 3 voting algorithm and self diagnostic ability. The Processor module of the system(SIDG-3000) is developed based on 32 Bit industrial microprocessor, which guaranteed high quality of the module and SRAM for data also SRAM for command are separated. The process module also includes inter process communication function and power back up function (SRAM for back-up). System reliability is estimated by using the model of Markov process. It is shown that the reliability of triplex system in mission time can be dramatically improved compared with a single control system Designed digital governor system is applied after modelling of the steam turbine generator system of Buk-Cheju Thermal Power Plant. Simulation is carried out to prove the effectiveness of the designed digital governor system

A Study on the Design and Performance Evaluation Technology of Fieldbus Pneumatic Solenoid Valve/Sensor System (필드버스 공압 솔레노이드 밸브/센서시스템 설계 및 성능평가 특성해석)

  • Kim, D.S.;Hong, C.P.
    • Proceedings of the KSME Conference
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    • 2001.11a
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    • pp.865-870
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    • 2001
  • For pneumatic system control, we need a data transmission system with high speed and high reliability or information interchange between main computer and solenoid valves and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid valves. In addition we developed a communication protocol for construction of RS-485 based multidrop network, and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. The field test results show that, even under high noise environment, the data transmission of 375Kbps rate is possible up to 1,000m without using repeater. In addition, the system developed in this research is proved to be used easily for extension of a communication network because of its module structure.

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Defects and Electrical Properties of NiO and Co3O4-doped ZnO-Bi2O3-Sb2O3 Ceramics (NiO와 Co3O4를 첨가한 ZnO-Bi2O3-b2O3 세라믹스의 결함과 전기적 특성)

  • Hong, Youn-Woo;Lee, Young-Jin;Kim, Sei-Ki;Kim, Jin-Ho
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.1
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    • pp.38-43
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    • 2013
  • In this study we aims to examine the effects of $Co_3O_4$ and NiO doping on the defects and electrical properties in ZnO-$Bi_2O_3-Sb_2O_3$ (Sb/Bi=0.5) varistors. It seemed to form ${Zn_i}^{{\cdot}{\cdot}}$(0.20 eV) and ${V_o}^{\cdot}$(0.33 eV) as dominant defects in Co and Ni co-doped ZBS system, however only ${V_o}^{\cdot}$ appeared in Co- or Ni-doped ZBS. Even though the same defects it was different in capacitance (1.5~4.5 nF) and resistance ($0.3{\sim}9.5k{\Omega}$). The varistor characteristics were improved with Co and Co+Ni doping (non-linear coefficient, ${\alpha}$= 36 and 29, relatively) in ZBS. The various parameters ($N_d=1.43{\sim}2.33{\times}10^{17}cm^{-3}$, $N_t=1.40{\sim}2.28{\times}10^{12}cm^{-2}$, ${\Phi}b$=1.76~2.37 V, W= 98~118 nm) calculated from the C-V characteristics in our systems did not depend greatly on the type of dopant, which were in the range of a typical ZnO varistors. It should be derived a improved C-V equation carefully for more reliable parameters because the variation of the varistor capacitance as a function of the applied dc voltage is depend on the defect, frequency, and temperature.

Chromatic Number Algorithm for Exam Scheduling Problem (시험 일정 계획 수립 문제에 관한 채색 수 알고리즘)

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.4
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    • pp.111-117
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    • 2015
  • The exam scheduling problem has been classified as nondeterministic polynomial time-complete (NP-complete) problem because of the polynomial time algorithm to obtain the exact solution has been unknown yet. Gu${\acute{e}}$ret et al. tries to obtain the solution using linear programming with $O(m^4)$ time complexity for this problem. On the other hand, this paper suggests chromatic number algorithm with O(m) time complexity. The proposed algorithm converts the original data to incompatibility matrix for modules and graph firstly. Then, this algorithm packs the minimum degree vertex (module) and not adjacent vertex to this vertex into the bin $B_i$ with color $C_i$ in order to exam within minimum time period and meet the incompatibility constraints. As a result of experiments, this algorithm reduces the $O(m^4)$ of linear programming to O(m) time complexity for exam scheduling problem, and gets the same solution with linear programming.

QEMU/KVM Based In-Memory Block Cache Module for Virtualization Environment (가상화 환경을 위한 QEMU/KVM 기반의 인메모리 블록 캐시 모듈 구현)

  • Kim, TaeHoon;Song, KwangHyeok;No, JaeChun;Park, SungSoon
    • Journal of KIISE
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    • v.44 no.10
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    • pp.1005-1018
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    • 2017
  • Recently, virtualization has become an essential component of cloud computing due to its various strengths, including maximizing server resource utilization, easy-to-maintain software, and enhanced data protection. However, since virtualization allows sharing physical resources among the VMs, the system performance can be deteriorated due to device contentions. In this paper, we first investigate the I/O overhead based on the number of VMs on the same server platform and analyze the block I/O process of the KVM hypervisor. We also propose an in-memory block cache mechanism, called QBic, to overcome I/O virtualization latency. QBic is capable of monitoring the block I/O process of the hypervisor and stores the data with a high access frequency in the cache. As a result, QBic provides a fast response for VMs and reduces the I/O contention to physical devices. Finally, we present a performance measurement of QBic to verify its effectiveness.

A Design of Gateway for Industrial Communication (산업용 통신 게이트웨이 설계)

  • Eum, Sang-hee;Lee, Byong-hoon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.281-283
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    • 2016
  • Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

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An I/O Bus-Based Dual Active Fault Tolerant Architecture fort Good System Performance

  • Kwak, Seung-Uk;Kim, Jeong-Il;Jeong, Keun-Won;Park, Kyong-Bae;Kang, Kyong-In;Kim, Hyen-Uk;Lee, Kwang-Bae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.06a
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    • pp.515-520
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    • 1998
  • In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

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Implementation and Performance Measurement of Personal Media Gateway for Applications over BcN Networks (BcN용 미디어 프로세서형 단말(PMG)의 구현 및 성능시험)

  • Jang, Seong-Hwan;Yang, Soo-Kyung;Cha, Young;Choi, Woo-Suk;Son, Seok-Bae;Kim, Jung-Joon
    • 한국정보통신설비학회:학술대회논문집
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    • 2005.08a
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    • pp.329-332
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    • 2005
  • In this paper, we describe implementation of personal media gateway (PMG) for applications over BcN networks. PMG is a TV based set-top terminal, which enables transmission of Full D1 high quality video and audio at the speed of maximum 2Mbps. It supports SIP protocol and QoS for the BcN networks. The hardware of the PMG consists of host module, audio/video codec processing module, DTMF module, and remote control I/O module. H.263 and MPEG4 software are implemented in DSP as codec for hi-directional communication and streaming, respectively. G.711 and Ogg-Vorbis are implemented as audio codec. We examined the quality of video using the Video Quality Test Equpment, which was developed by KT Convergence Lab. The experimental results show the video quality of MOS 4.1 and audio quality of MOS 4.3. We expect that PMG will be prospective business models, and create new customer value.

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VME bus based control system for step & scan exposure tool (VME bus를 이용한 Step & Scan형 노광장비의 Control System 구성)

  • 최용만;오병주;김도훈;정해빈
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.672-675
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    • 1997
  • This paper proposes a structure of the control system for the step & scan exposure tool. The step & scan exposure tool is used for the manufacturing process of the semiconductor DRAM memory of giga bit. The control system employs the VME bus instead of the conventional ISA bus so that all control signals and data can be managed separately by the 4 VME-PCs for fast and fault-free flow of signals for multi-tasking. A high speed I/O card is equipped for the real-time monitoring and control of the sub module equipment. Then all the subsystems are integrated and aligned for the operation of the step & scan exposure tool with the VME bus and, I/O card.

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