• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.10
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• pp.1279-1286
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• 2021

The electrocardiogram (ECG) signal is a good indicator for early diagnosis of heart abnormalities. The ECG signal has a different reference normal signal for each person. And it requires lots of data to diagnosis. In this paper, we propose an adaptive OpenCL-based FPGA-GPU hybrid-layer platform to efficiently accelerate ECG signal diagnosis. As a result of diagnosing 19870 number of ECG signals of MIT-BIH arrhythmia database on the platform, the FPGA accelerator takes 1.15s, that the execution time was reduced by 89.94% and the power consumption was reduced by 84.0% compared to the software execution. The GPU accelerator takes 1.87s, that the execution time was reduced by 83.56% and the power consumption was reduced by 62.3% compared to the software execution. Although the proposed FPGA-GPU hybrid platform has a slower diagnostic speed than the FPGA accelerator, it can operate a flexible algorithm according to the situation by using the GPU.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.257-266
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• 2006

Recently TCP/IP Offload Engine (TOE) technology, which processes TCP/IP on a network adapter instead of the host CPU, has become an important approach to reduce TCP/IP processing overhead in the host CPU. There have been two approaches to implementing TOE: software TOE, in which TCP/IP is processed by an embedded processor on a network adapter; and hardware TOE, in which all TCP/IP functions are implemented by hardware. This paper proposes a hybrid TOE that combines software and hardware functions in the TOE. In the hybrid TOE, functions that cannot have guaranteed performance on an embedded processor because of heavy load are implemented by hardware. Other functions that do not impose as much load are implemented by software on embedded processors. The hybrid TOE guarantees network performance near that of hardware TOE and it has the advantage of flexibility, because it is easy to add new functions or offload upper-level protocols of TCP/IP. In this paper, we developed a prototype board with an FPGA and an ARM processor to implement a hybrid TOE prototype. We implemented the hardware modules on the FPGA and the software modules on the ARM processor. We also developed a coprocessing mechanism between the hardware and software modules. Experimental results proved that the hybrid TOE prototype can greatly reduce the load on a host CPU and we analyzed the effects of the coprocessing mechanism. Finally, we analyzed important features that are required to implement a complete hybrid TOE and we predict its performance.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.05a
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• pp.51-54
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• 2003

진화하드웨어는 하드웨어 스스로 진화하여 필요한 회로를 구성한다 회로를 재구성하기 위해서 유전자 알고리즘을 사용한다. 유전자 알고리즘(Genetic Algorithm)은 전역적 탐색을 통하여 해를 구한다. 하지만 유전자 알고리즘은 많은 개체의 평가를 통하여 이루어지기 때문에 수행하는데 시간이 많이 소요된다. 이전의 연구에서 유전자 알고리즘 프로세서를 이용하여 진화하드웨어를 구성했다. 유전자 알고리즘 프로세서는 유연성이 떨어지고 범용적으로 사용하기 어렵다. 본 논문에서는 CPU를 이용하여 유전자 알고리즘 프로세서를 소프트웨어로 제어하는 방법을 제안한다 소프트웨어로 합성한 신호로 GAP의 동작을 제어하기 때문에 유연성을 가질 수 있다 FPGA에 CPU와 유전자 알고리즘 프로세서를 구현하여 one-chip 하드웨어를 구현한다.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1151-1172
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• 2014

This paper presents a user programmable computational/control platform developed to conduct real-time hybrid simulation (RTHS). The architecture of this platform is based on the integration of a real-time controller and a field programmable gate array (FPGA).This not only enables the user to apply user-defined control laws to control the experimental substructures, but also provides ample computational resources to run the integration algorithm and analytical substructure state determination in real-time. In this platform the need for SCRAMNet as the communication device between real-time and servo-control workstations has been eliminated which was a critical component in several former RTHS platforms. The accuracy of the servo-hydraulic actuator displacement control, where the control tasks get executed on the FPGA was verified using single-degree-of-freedom (SDOF) and 2 degrees-of-freedom (2DOF) experimental substructures. Finally, the functionality of the proposed system as a robust and reliable RTHS platform for performance evaluation of structural systems was validated by conducting real-time hybrid simulation of a three story nonlinear structure with SDOF and 2DOF experimental substructures. Also, tracking indicators were employed to assess the accuracy of the results.

• Journal of Broadcast Engineering
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• v.21 no.4
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• pp.621-629
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• 2016

This paper suggests a new structure of hybrid DRC to enhance the psychoacoustic sound quality of a conventional multiband DRC. The proposed hybrid DRC consists of two serially cascaded stages. The front stage DRC is multiband, and it compresses input based on RMS level detection, whereas, the back stage DRC is single band, and it regulates input according to peak level detection. The proposed hybrid DRC shows better loudness while suppressing distortion by clipping. The proposed algorithm was verified through MATLAB simulation, and it was implemented using an FPGA board for listening test. The test result showed that the proposed hybrid structure enhances overall psychoacoustic sound quality compared to conventional structures, which is based on only RMS or peak level detection.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.450-453
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• 2017

In this abstract, the FPGA system using solar tracking is introduced. Solar tracking system combined with sensor tracking and solar altitude programming is utilized. The sensor tracking system consists of image sensor, light sensor, and the programs for sun altitude received by the computer. The sun altitude is received from the national weather database by wireless communication. The goal is to have maximum energy generation efficiency using bi-directional tracking and mixed tracking with FPGAs that are relatively inexpensive in terms of developing and programming the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.56-64
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• 2007

We developed the first automatic design system targeting a promising hybrid CMOS-Nanoelectronics Architecture called CMOL. The CMOL architecture uses NOR gates to implement combinational logic. In this hybrid CMOS-nanoelectronics architecture, logical functions and the interconnections share the nanoelectronics hardware resource. Towards automating the CMOL physical design process, we developed a model for the CMOL architecture, formulated the placement and routing problems for the CMOL architecture subject to the unique CMOL specific constraints, and solved it by combining a placement algorithm with a gate assignment algorithm in a loop. We validated the proposed approach by implementing several industrial strength designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.57-68
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• 2016

In this study, we present the modern hybrid system based power generation for electric vehicle applications. We describe the hybrid structure of modified current source based DC - DC converters used to extract the maximum power from Photovoltaic (PV) and Fuel Cell system. Due to reduced dc-link capacitor requirement and higher reliability, the current source inverters (CSI) better compared to the voltage source based inverter. The novel control strategy includes Distributed Maximum Power Point Tracking (DMPPT) for photovoltaic (PV) and fuel cell power generation system. The proposed DC - DC converters have been analyzed in both buck and boost mode of operation under duty cycle 0.5>d, 0.5<d<1 and 0.5<d for capable electric vehicle applications. The proposed topology benefits include one common DC-AC inverter that interposes the generated power to supply the charge for the sharing of load in a system of hybrid supply with photovoltaic panels and fuel cell PEM. An improved control of Direct Torque and Flux Control (DTFC) based induction motor fed by current source converters for electric vehicle.In order to achieve better performance in terms of speed, power and miles per gallon for the expert, to accepting high regenerative braking current as well as persistent high dynamics driving performance is required. A simulation model for the hybrid power generation system based electric vehicle has been developed by using MATLAB/Simulink. The Direct Torque and Flux Control (DTFC) is planned using Xilinx ISE software tool in addition to a Modelsim 6.3 software tool that is used for simulation purposes. The FPGA based pulse generation is used to control the induction motor for electric vehicle applications. FPGA has been implemented, in order to verify the minimal error between the simulation results of MATLAB/Simulink and experimental results.