• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.30-37
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• 1993

In this paper, we present a simple and general lifetime prediction model for PMOSFET by using the correlation between transconductance degradation and gate current influence to solve a problem that that I$_{b}$ is dependent on drain structure. The suggested model is applied to a different channel, drain structured PMOSFET. For all PMOSFETs, dg$_{m}$/g$_{m}$ of PMOSFET appears with one straight line about Q$_{g}$, therefore, this model using I$_{g}$ is consistent with experiment result independently of channel, drain structure. It is, therefore, proposed that a model using I$_{g}$ has a general applicability for PMOSFET's.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.51-54
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• 1996

This paper reports the studies of the inversion layer mobility in p-channel Si MOSFET's under hot-carrier degradated condition. The validity of relationship of hot carrier degradations between the surface effective mobility and field effect mobility and are examined. The effective mobility(${\mu}$$\_$eff/) is derived from the channel conductances, while the field-effect mobility(${\mu}$$\_$FE/) is obtained from the transconductance. The characteristics of mobility curves can be divided into the 3 parts of curves. It was reported that the mobility degradation is due to phonon scattering, coulombic scattering and surface roughness. We are measured the mobility slope in curves with DC-stress [V$\_$g/=-3.1v]. It was found that the mobility(${\mu}$$\_$eff/ and ${\mu}$$\_$FE/) of p-MOSFET's was increased by increasing stress time and decreasing channel length. Because of the increasing stress time and increasing V$\_$g/ is changed oxide reliability and increased vertical field.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.9
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• pp.736-742
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• 1991

N$^{+}$poly gate NMOSFETs and p$^{+}$ poly gate (surface type) PMOSFETs with three different gate oxides(SiO2, NO, and ONO) were fabricated. The rapid thermal nitridation and reoxidation techniques have been applied to gate oxide formation. The current drivability of the ONO NMOSFET shows larger values than that of the SiO2 NMOSFET. The snap-back occurs at a lower drain voltage for SiO$_2$ cases for ONO NMOSFET. Under the maximum substrate current bias conditions, hot-carrier effects inducting threshold voltage shift and transconductance degradation were investigated. The results indicate that ONO films exhibit less degradation in terms of threshold voltage shift. It was confirmed that the ONO samples achieve good improvement of hot-carrier immunity. In a SiO$_2$ SC-PMOSFET, with significant boron penetration, it becomes a depletion type (normally-on). But ONO films show excellent impurity barrier properties to boron penetration from the gate.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.2
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.3
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• pp.6-11
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• 1977

The noise behavior of the Schottky Barrier Gate FET has been investigated by the use of noise equivalent circuit. It has been found that an additional noise source has to be taken into account in the GaAs SBGFET's biased in the pinch-off region; the intervalley scattering noise and the hot electron noise. In this paper, a noise equivalent circuit has been used to determine the noise parameter which was taken into account influence of the saturation velocity of carrier and parasitic resistance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.869-873
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• 2001

The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.59-66
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• 1995

The hot electron induced effective channel length modulation (${\Delta}L_{H}$) and HEIP characteristics in PMOSFET's after bidirectional stress are presented. Trapped electron charges in gate oxide and lateral field are calculated from the gate current model, and ${\Delta}L_{H}$(${\Delta}L_{HD},\;{\Delta}L_{HS}$) is calculated using trapped electron charges and lateral field. It has been found that ${\Delta}I_{d}$and ${\Delta}L_{H}$ are more affected by the stress order (Forward-Reverse of Reverse or Reverse-Forward) than the stress direction, and they vary logarithmically with the stress time. In contrast, ${\Delta}V_{t}$ and ${\Delta}V_{pt}$ are more affected by the stress direction thatn the stress order. The correlation between ${\Delta}V_{pt}$ and the stress time can be explanined as the following polynomial functin: ${\Delta}V_{pt}$=AT$^{n}$. It has also been shown that PMOSFET degradation is related with the gate current and the effects of ${\Delta}V_{pt}$ is the most significant.

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.876-879
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• 1996

The effect of oxygen vacancy and Sn donor on carrier density for Indium Tin oxide (ITO) and Indium oxide (InO) films has been investigated. Hot-cathode Penning discharge sputtering (HC-PDS) in the mixed gasses of argon and oxygen was applied to fabricate the ITO and InO films. Density of oxygen vacancy was estimated using a high-energy ion beam technique. The electrical properties of the films such as resistivity, carrier density and mobility were estimated by Van der Pauw method. The doping efficiency of oxygen vacancy could be obtained from the relationship between oxygen vacancy and carrier density. The doping efficiency of oxygen vacancy for ITO films resulted in a quite small value. Comparing the doping efficiencies of ITO and InO films, the effect of Sn donor on carrier density was also discussed.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.193-196
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• 1987

We reported that hot electron phenomena in submicron nMOSFET by Monte Carlo method. In order to predict the influence of the hot electron effects on the device reliability, either simple analytical model or a complete two dimensional numerical simulation has been adopted. Results of numerical simulation, based on the static mobility model, may be inaccurate when gate length of MOSFET is scaled down to less than 1um. Most of device simulation packages utilize the static nobility model. Monte Carlo method based on stochastic analysis of carrier movement may be a powerful tool to characterize hot electrons. In this work, energy and velocity distribution of carriers were obtained to predict the relative degree of short channel effects for different device parameters. Our analysis shows a few interesting results when $V_{ds}$ is 5 volt, average electron energy does not increase with gate bias as evidenced by substrate current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.