• IEIE Transactions on Smart Processing and Computing
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• v.4 no.4
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• pp.291-296
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• 2015

This paper describes the design of a high-speed comparator for high-speed automatic test equipment (ATE). The normal comparator block, which compares the detected signal from the device under test (DUT) to the reference signal from an internal digital-to-analog converter (DAC), is composed of a rail-to-rail first pre-amplifier, a hysteresis amplifier, and a third pre-amplifier and latch for high-speed operation. The proposed continuous comparator handles high-frequency signals up to 800MHz and a wide range of input signals (0~5V). Also, to compare the differences of both common signals and differential signals between two DUTs, the proposed differential mode comparator exploits one differential difference amplifier (DDA) as a pre-amplifier in the comparator, while a conventional differential comparator uses three op-amps as a pre-amplifier. The chip was implemented with $0.18{\mu}m$ Bipolar CMOS DEMOS (BCDMOS) technology, can compare signal differences of 5mV, and operates in a frequency range up to 800MHz. The chip area is $0.514mm^2$.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.1-7
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• 2014

This paper describes the implementation of high speed comparator for the ATE (automatic test equipment) system. The comparator block is composed of continuous comparator, differential difference amplifier(DDA) and output stage. For the wide input dynamic range of 0V to 5V, and for the high speed operation (1~800MHz), high speed rail-to-rail amplifier is used in the first stage. And hysteresis circuits, pre-amp and latch are followed for high speed operation. To measure the difference of output signals between the two devices under test (DUTs), a DDA is applied because it can detect the differences of both common signals and differential signals. This comparator chip was implemented with $0.18{\mu}m$ BCDMOS process and can compare the signal difference of 5mV up to the frequency range of 800 MHz. The chip area of the comparator is $620{\mu}m{\times}830{\mu}m$.

• Journal of the Korea Society of Computer and Information
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• v.24 no.2
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• pp.57-66
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• 2019

This paper compared the performance with an overview of channel equalization techniques used in high-speed serial transceivers, including the homogeneous architecture and associated components for the GHz interconnect of backplane and cable channels. It also used the MATLAB tool to present system analysis and simulation results for continuous time equivalent structures. In the case of conventional continuous equalization, high frequency deficits occur due to the use of a comparator that is difficult to implement as well as the low speed limit. In this paper, the channel equalization technique based on the power spectrum analysis of clocks was used to compensate for the frequency loss, and the application of the TX+Channel and TX+Equalizer filters enabled the measurement of attenuation and equivalence without comparators. The application of blender and band-pass filters at high speeds also showed significant effectiveness.