• 제목/요약/키워드: High-k thin film transistor

검색결과 207건 처리시간 0.033초

High Performance Thin-Film Transistors Based on Zinc Oxynitride Semiconductors: Experimental and First-Principles Studies

  • Kim, Yang-Soo;Kim, Jong Heon;Kim, Hyun-Suk
    • 한국재료학회지
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    • 제26권1호
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    • pp.42-46
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    • 2016
  • The properties of zinc oxynitride semiconductors and their associated thin film transistors are studied. Reactively sputtered zinc oxynitride films exhibit n-type conduction, and nitrogen-rich compositions result in relatively high electron mobility. Nitrogen vacancies are anticipated to act as shallow electron donors, as their calculated formation energy is lowest among the possible types of point defects. The carrier density can be reduced by substituting zinc with metals such as gallium or aluminum, which form stronger bonds with nitrogen than zinc does. The electrical properties of gallium-doped zinc oxynitride thin films and their respective devices demonstrate the carrier suppression effect accordingly.

Highly Crystalline 2,6,9,10-Tetrakis((4-hexylphenyl)ethynyl)anthracene for Efficient Solution-Processed Field-effect Transistors

  • Hur, Jung-A;Shin, Ji-Cheol;Lee, Tae-Wan;Kim, Kyung-Hwan;Cho, Min-Ju;Choi, Dong-Hoon
    • Bulletin of the Korean Chemical Society
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    • 제33권5호
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    • pp.1653-1658
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    • 2012
  • A new anthracene-containing conjugated molecule was synthesized through the Sonogashira coupling and reduction reactions. 1-Ethynyl-4-hexylbenzene was coupled to 2,6-bis((4-hexylphenyl) ethynyl)anthracene-9,10-dione through a reduction reaction to generate 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene. The semiconducting properties were evaluated in an organic thin film transistor (OTFT) and a single-crystal field-effect transistor (SC-FET). The OTFT showed a mobility of around 0.13 $cm^2\;V^{-1}\;s^{-1}$ ($I_{ON}/I_{OFF}$ > $10^6$), whereas the SC-FET showed a mobility of 1.00-1.35 $cm^2\;V^{-1}\;s^{-1}$, which is much higher than that of the OTFT. Owing to the high photoluminescence quantum yield of 2,6,9,10-tetrakis((4-hexylphenyl)ethynyl) anthracene, we could observe a significant increase in drain current under irradiation with visible light (${\lambda}$ = 538 nm, 12.5 ${\mu}W/cm^2$).

ZnO-based thin-film transistor inverters using top and bottom gate structures

  • Oh, Min-Suk;Kim, Yong-Hoon;Park, Sung-Kyu;Han, Jeong-In;Lee, Ki-Moon;Im, Seong-Il;Lee, Byoung-H.;Sung, Myung-M.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.461-463
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    • 2009
  • We report on the fabrication of ZnO-based thin-film transistor (TFT) inverters with top and bottom gate structures with $Al_2O_3$ dielectrics grown by atomic layer deposition (ALD). Since the top gate ZnO-based TFT showed somewhat lower field effect mobility than that of the bottom gate device, our ZnO-based TFT inverters were designed with identical dimensions for both channels. This TFT inverter device demonstrated an high voltage gain at a low supply voltage of 5 V and clear dynamic behavior.

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촉매반응 화학기상증착법을 이용한 유기발광소자의 박막 봉지 (Thin Film Passivation of Organic Light Emitting Diodes by Catalyzer Enhanced Chemical Vapor Deposition (CECVD))

  • 김한기;문종민;배정혁;정순욱;김명수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.71-72
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    • 2006
  • We report on plasma damage free chemical vapor deposition technique for the thin film passivation of organic light emitting diodes (OLEDs), organic thin film transistor (OTFT) and flexible displays using catalyzer enhanced chemical vapor deposition (CECVD). Specially designed CECVD system has a ladder-shaped tungsten catalyzer and movable electrostatic chuck for low temperature deposition process. The top emitting OLED with thin film $SiN_x$ passivation layer shows electrical and optical characteristics comparable to those of the OLED with glass encapsulation. This indicates that the CECVD technique is a promising candidate to grow high-quality thin film passivation layer on OLED, OTFT, and flexible displays.

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OFF 전류의 감소를 위한 다결정 실리콘 박막 트랜지스터의 구조 연구 (A Study on the Structure of Polycrystalline Silicon Thin Film Transistor for Reducing Off-Current)

  • 오정민;민병혁;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 B
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    • pp.1292-1294
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    • 1993
  • This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

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Anneal Temperature Effects on Hydrogenated Thin Film Silicon for TFT Applications

  • Ahn, Byeong-Jae;Kim, Do-Young;Yoo, Jin-Su;Junsin Yi
    • Transactions on Electrical and Electronic Materials
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    • 제1권2호
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    • pp.7-11
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    • 2000
  • a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

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램프 스캐닝 열처리에 의한 다결정 실리콘 박막의 형성 및 TFT 제작에 관한 연구 (A Study on the Formation of Polycrystalline Silicon Film by Lamp-Scanning Annealing and Fabrication of Thin Film Transistors)

  • 김태경;김기범;이병일;주승기
    • 전자공학회논문지D
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    • 제36D권1호
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    • pp.57-62
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    • 1999
  • 유리기판 위에 다결정 실리콘 박막 트랜지스터(Thin Film Transistor, TFT)를 형성하기 위해서 램프 Scanning 열처리 장치를 개발하였다. 선형 램프를 Scanning 함으로써 대면적 유리기판에의 적용 가능성을 높였으며 TFT의 채널 부분은 금속 유도 측면 결정화 방법에 의해 결정화 시켰다. 할로겐 램프에 의한 빛은 투명 유리기판은 가열시키지 않고 ,island 행태의 실리콘 박막만을 가열시킬 수 있었다. 실리콘 산화막으로 이루어진 Capping layer를 적용하였고 이때의 성장 속도는 Capping layer가 없는 경우보다 35배 정도로 빠른 MILC 성장 속도를 나타내었다. 할로겐 램프를 약 1.4mm/sec의 속도록 Scanning한 경우 유리기판의 손상 없이 18-27${\mu}m/scan$ 정도의 결정화를 나타내었다. 이와 같이 제작된 다결정 실리콘 박막으로 제작된 TFT는 전자이동도 130$cm^2/V{\cdot}sec$의 우수한 특성을 나타내었다.

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NH3 Plasma Treatment를 사용한 고성능 TFT 제작 및 분석 (A Production and Analysis on High Quality of Thin Film Transistors Using NH3 Plasma Treatment)

  • 박희준;;이준신
    • 한국전기전자재료학회논문지
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    • 제30권8호
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    • pp.479-483
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    • 2017
  • The effect of $NH_3$ plasma treatment on device characteristics was confirmed for an optimized thin film transistor of poly-Si formed by ELA. When C-V curve was checked for MIS (metal-insulator-silicon), Dit of $NH_3$ plasma treated and MIS was $2.7{\times}10^{10}cm^{-2}eV^{-1}$. Also in the TFT device case, it was decreased to the sub-threshold slope of 0.5 V/decade, 1.9 V of threshold voltage and improved in $26cm^2V^{-1}S^{-1}$ of mobility. Si-N and Si-H bonding reduced dangling bonding to each interface. When gate bias stress was applied, the threshold voltage's shift value of $NH_3$ plasma treated device was 0.58 V for 1,000s, 1.14 V for 3,600s, 1.12 V for 7,200s. As we observe from this quality, electrical stability was also improved and $NH_3$ plasma treatment was considered effective for passivation.

선결정화법을 이용한 금속 유도 일측면 결정화에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성 개선 효과 (Dynamic Characteristics of Metal-induced Unilaterally Crystallized Polycrystalline Silicon Thin-film Transistor Devices and Circuits Fabricated with Precrystallization)

  • 황욱중;강일석;김영수;양준모;안치원;홍순구
    • 한국진공학회지
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    • 제17권5호
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    • pp.461-465
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    • 2008
  • 적층 박막 내에서의 상변화는 주변 층에 영향을 준다. 결정화가 게이트 절연층에 주는 영향이 제거된 선결정화법(precrystallization)이 금속 유도 일측면 결정화(metal-induced unilateral crystallization)에 의해 제작된 다결정 실리콘 박막 트랜지스터 소자 및 회로의 전기적 특성에 미치는 영향에 대하여 연구하였다. 이 방법으로 만들어진 소자는 일반적인 후 결정화(postcrystallization) 소자에 비하여 높은 전류 구동력을 보였다. 여기에 본 연구는 DC bias에 의한 ring oscillator의 특성 변화를 연구하였다. 선결정화된 실리콘 박막을 이용하여 제작한 PMOS inverter는 후결정화된 실리콘 박막을 이용하여 제작한 inverter에 비하여 매우 동적(dynamic)이고도 안정적인 특성을 보였다.