• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• 대한전기학회논문지:시스템및제어부문D
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• 제55권5호
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• pp.229-235
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• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• 전자공학회논문지CI
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• 제41권4호
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• pp.41-49
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• 2004

본 논문은 FPGA 임베디드 기가비트 트랜시버의 테스트에 관한 방법과 측정 결과를 다룬다. 실험에 사용한 디바이스는 Altera 사의 Stratix GX 디바이스로 범용 고속 프로토콜을 지원하는 트랜시버(GXB)이다. 본 논문은 차세대 IO 버스로 대두되는 PCI Express 직렬 프로토콜을 GXB에 구현하였다. PCI Express 규격에 맞게 생성된 GXB 모듈은 타이밍 시뮬레이션을 거쳐 하드웨어 구현과 테스트를 수행하였다. 트랜시버 테스트 방법으로 GXB 내부 블록 테스트, GXB 신호 무결성 테스트, GXB 입출력 버퍼 및 온칩 터미네이션 테스트, GXB 프로토콜 테스트의 네 가지 검증 절차를 거쳤다. 본 논문을 통해 FPGA 임베디드 트랜시버의 설계방법과 테스트 절차, 측정 결과를 제시한다.

• 한국정보처리학회논문지
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• 제4권2호
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• pp.499-514
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• 1997

본 논문에서는 다양한 이기종 망간의 상호 연동을 통한 개방형정보통신서비스를 제공하기 위해 게이트웨이시스(Gateway System)으로 개발되고 있는 대용량 통신처리 시스템의 내부 고속 연동망의 구조를 제시한다. 주요제원으로는 32*32 입출력 체널의 공유버스 스위칭 대역폭은은 640MBPS로써 평형상태에서 각 채널별 약 20Mbps 정도의 대연폭 할당이 가능하여 전화망 뿐만 아니라 고속의 ISDN 및 인터네트 서비스 연동이 가능하다. 고속 연동망은 주된 스위칭 기능을 담당하는 중재교환부, 각 입출력 채널을 구성하는 가입자 입출력부, 이들 상호 연결하는 백플레인버스로 구성이 되고, 신뢰성 향상기 위하여 부하 분담 방식의 이중화 구성이 가능하다.또한망정합모들의 구현을 용이케 하고 연동망 프로토콜을 처리하는 부하를 감소하기 위해 고속 연동망 프로토콜을 전담 처리 가입자노드 어댑터를 개발하였다.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• 대한임베디드공학회논문지
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• 제14권1호
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.663-665
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• 2000

For the control system of thermal turbine in fuel and nuclear power plant, as high reliability and availability are required, redundant control system is generally applied. This paper presents the configuration and design of such a redundant control system that can be suitable for control and monitoring of the turbine. System components such as I/O system, communication networks, voting system are designed, and especially the new intelligent voter using serial communication are proposed. The characteristics of the implemented control system is independence of the control, protection and monitoring functions, and discrimination of the redundancies, and high availability. The control functions such as speed control, load control, valve control and protective functions such as overspeed and PLU are designed in detail.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1152-1156
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• 2003

For pneumatic valve system control, we need a serial data transmission system with high speed and reliability for information interchange between main computer and I/O devices. This paper presents a set of design techniques for a data communication system that is mainly used for pneumatic valve system control. For this purpose, we first designed hardware modules for an interface between central control module and local node that handles the operation of solenoid control valves. in addition, we developed a communication protocol for construction of rs-485 based multi-drop network and this protocol is basically designed with a kind of polling technique. Finally we evaluated performance of the developed system. the field test results show that, even under high noise environment, the data transmission of 375kbps rate is possible up to 1,500meter without using repeater. In addition, the system developed in this research is easily to be extended for a communication network because of its modular structure.

• 전자공학회논문지A
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• 제32A권12호
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• pp.108-114
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• 1995

Recently, along wtih the advance of high-performance system, synchronous DRAM's (SDRAM's) which provide consecutive data output synchronized with an external clock signal, have been reported. However, in the conventional SDRAM's which utilize a multi-stage serial pipelined scheme, the column path is divided into multi-stages depending on CAS latency N. Thus, as the operating speed and CAS latency increase, new stages must be added, thereby causing a large area penalty due to additinal latches and I/O lines. In the proposed register-based parallel pipelined scheme, (N-1) registers are located between the read data bus line pair and the data output buffer and the coming data are sequentially stored. Since the column data path is not divided and the read data is directly transmitted to the registers, the busrt read operation can easily be achieved at higher frequencies without a large area penalty and degradation of internal timing margin. Simulation results for 0.32um-Tech. 4-Bank 64M SDRAM show good operation at 200MHz and an area increment is less than 0.1% when CAS latency N is increased from 3 to 4.. This pipelined scheme is more advantageous as the operating frequency increases.