• 제목/요약/키워드: High-Dielectric

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Dielectric Properties of Orthorhombic Dysprosium Manganites

  • Wang, Wei Tian
    • 한국재료학회지
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    • 제29권12호
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    • pp.753-756
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    • 2019
  • Orthorhombic dysprosium manganite DyMnO3 with single phase is synthesized using solid-state reaction technique and the crystal structure and dielectric properties as functions of temperature and frequency are investigated. Thermally activated dielectric relaxations are shown in the temperature dependence of the complex permittivity, and the respective peaks are found to be shifted to higher temperatures as the measuring frequency increases. In Arrhenius plots, activation energies of 0.32 and 0.24 eV for the high- and low-temperature relaxations are observed, respectively. Analysis of the relationship between the real and imaginary parts of the permittivity and the frequencies allows us to explain the dielectric behavior of DyMnO3 ceramics by the universal dielectric response model. A separation of the intrinsic grain and grain boundary properties is achieved using an equivalent circuit model. The dielectric responses of this circuit are discerned by impedance spectroscopy study. The determined grain and grain boundary effects in the orthorhombic DyMnO3 ceramics are responsible for the observed high- and low-temperature relaxations in the dielectric properties.

유전체를 활용한 초고속 에너지 충/방전 소자 기술 (Recent Progress in Dielectric-Based Ultrafast Charging/Discharging Devices)

  • 최현수;류정호;윤운하;황건태
    • 한국전기전자재료학회논문지
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    • 제35권4호
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    • pp.322-332
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    • 2022
  • Energy storage capacitors based on dielectric ceramics with superior polarization properties and dielectric constant can provide much higher output power density due to their very fast energy charging/discharging rates, which are particularly suitable for operating pulsed-power devices. For an outstanding energy storage performance of dielectric capacitor, a large recoverable energy density could be derived by introducing a slim polarization-electric field hysteresis loop into dielectric materials by various technical approaches. Many research teams have explored various dielectric capacitor technologies to demonstrate high output power density and ultrafast charging/discharging behavior. This article reviews the recent research progress in high-performance dielectric capacitors for pulsed-power electronic applications.

Trypsin 반응에 대한 용매의 유전상수 및 압력의 영향 (Effect of Pressure and Solvent Dielectric Constant on the Kinetic Constants of Trypsin-Catalyzed Reaction.)

  • 박현;지영민
    • 한국미생물·생명공학회지
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    • 제28권1호
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    • pp.26-32
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    • 2000
  • Electrostatic forces contribute to the high degree of enzyme transition state complementarity in enzyme catalyzed reaction and such forces are modified by the solvent through its dielectric constant and polar properties. The contributions of electrostatic interaction to the formation of ES complex and the stabilization of transition state of the trypsin catalyzed reaction were probed by kinetic studied with high pressure and solvent dielectric constant. A good correlation has been observed between the increase of catalytic efficiency of trypsin and the decrease of solvent dielectric constant. Activation volume linearly decreased as the dielectric constant of solvent decreased, which means the increase in the reaction rae. Moreover, the decrease of activation volume by lowering the solvent dielectric constant implies a solvent penetration of the active with and a reduction of electrostatic energy for the formation of dipole of the active site oxyanion hole. When the 야electric constant of the solvents was lowered to 4.7 unit, the loss of activation energy and that of free energy of activation were 2.262 KJ/mol and 3.169 KJ/mol, respectively. The results of this study indicate that the high pressure kinetics combined with solvent effects can provide unique information on enzyme reaction mechanisms, and the controlling the solvent dielectric constant can stabilize the transition state of the trypsin-catalyzed reaction.

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평면형 대기압 유전장벽방전장치의 제작 및 동작특성분석 (Fabrication of Atmospheric Coplanar Dielectric Barrier Discharge and Analysis of its Driving Characteristics)

  • 이기융;김동현;이호준
    • 전기학회논문지
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    • 제63권1호
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    • pp.80-84
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    • 2014
  • The discharge characteristics of Surface Dielectric Barrier Discharge (SDBD) reactor are investigated to find optimal driving condition with adjusting various parameter. When the high voltage with sine wave form is applied to SDBD source, successive pulsed current waveforms are observed owing to multiple ignitions through the long discharge channel and wall charge accumulation on the dielectric surface. The discharge voltage, total charge between dielectrics, mean energy and power are calculated from measured current and voltage according to electrode gap and dielectric thickness. Discharge mode transition from filamentary to diffusive glow is observed for narrow gap and high applied voltage case. However, when the diffusive discharge is occurred with high applied voltage, the actual firing voltage is always lower than that with low driving voltage. The $Si_3N_4$, $MgF_2$, $Al_2O_3$ and $TiO_2$ are considered for dielectric protection and high secondary electron emission coefficient. SDBD with $MgF_2$ shows the lowest breakdown voltage. $MgF_2$ thin film is proposed as a protection layer for low voltage atmospheric dielectric barrier discharge devices.

질화규소 재료의 고온 유전물성 평가 (High Temperature Dielectric Properties of Silicon Nitride Materials)

  • 최두현
    • 한국군사과학기술학회지
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    • 제10권3호
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    • pp.114-119
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    • 2007
  • Dielectric properties of quartz glass and $Si_3N_4$ are investigated using the waveguide method from room temperature to $800^{\circ}C$. For the case of dielectric constant, $Si_3N_4$ showed similar increase with quartz glass up to $300^{\circ}C$, but less increase from $300^{\circ}C$ to $800^{\circ}C$. For the case of loss tangent, those showed gradual increase with temperature except of some temperature points. The loss tangent of $Si_3N_4$ and quartz glass increased up to 18.2% and 12.5% respectively. Through these researches, high temperature dielectric properties of silicon nitride materials are characterized.

Suppression of Dielectric Loss at High Temperature in (Bi1/2Na1/2)TiO3 Ceramic by Controlling A-site Cation Deficiency and Heat Treatment

  • Lee, Ju-Hyeon;Lee, Geon-Ju;Pham, Thuy-Linh;Lee, Jong-Sook;Jo, Wook
    • 센서학회지
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    • 제29권1호
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    • pp.7-13
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    • 2020
  • Dielectric capacitors are integral components in electronic devices that protect the electric circuit by providing modulated steady voltage. Explosive growth of the electric automobile market has resulted in an increasing demand for dielectric capacitors that can operate at temperatures as high as 400 ℃. To surpass the operation temperature limit of currently available commercial capacitors that operate in temperatures up to 125 ℃, Bi1/2Na1/2TiO3 (BNT), which has a large temperature-insensitive dielectric response with a maximum dielectric permittivity temperature of 300 ℃, was selected. By introducing an intentional A-site cation deficiency and post-heat treatment, we successfully manage to control the dielectric properties of BNT to use it for high-temperature applications. The key feature of this new BNT is remarkable reduction in dielectric loss (0.36 to 0.018) at high temperature (300 ℃). Structural, dielectric, and electrical properties of this newly developed BNT were systematically investigated to understand the underlying mechanism.

Giga-Bit급 DRAM을 위한 고유전 $(Ba,Sr)Tio_3$박막 커패시터의 유전완화 특성에 대한 회로 모델 (A Circuit Model of the Dielectric Relaxation of the High Dielectric $(Ba,Sr)Tio_3$ Thin Film Capacitor for Giga-Bit Scale DRAMs)

  • 장병탁;차선용;이희철
    • 대한전자공학회논문지SD
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    • 제37권4호
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    • pp.15-24
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    • 2000
  • 고유전 커패시터의 유전완화 특성은 시간영역에서 나타나는 커패시터의 동적특성으로 이해될 수 있으며 이것은 DRAM의 재충전 시간동안 충전된 전하를 잃어버리는 가장 주된 요인으로 인식된다. 그러므로 DRAM 동작에 미치는 영향을 고려하기 위하여 고유전 커패시터의 유전완화에 대한 등가회로를 만드는 것이 필수적이다. 그러나 아직까지 등가회로를 만들 수 있는 일반적이고 이론적인 방법이 제시되지 않고 있다. 근 본 연구에서는 고유전 커패시터의 등가회로를 주파수 영역에서 모델링하는 새로운 방법을 개발하였다. 이 방법은 이론적인 체계를 갖춘 일반적인 방법이다. 또한, 본 연구에서는 실험과정을 통해서 이 방법의 타당성으로 확인하였고, 궁극적으로 새로운 방법으로 얻어진 등가회로를 활용하여 유전완화가 DRAM 동작에 미치는 영향을 고찰하였다.

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고온용 정전기척의 유전층 개발에 관한 연구 (A Study on Development of Dielectric Layers for High-Temperature Electrostatic Chucks)

  • 방재철
    • 마이크로전자및패키징학회지
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    • 제8권3호
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    • pp.31-36
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    • 2001
  • 고온용 정전기척(high-temperature electrostatic chuck, HTESC)에 적합한 특성의 유전재료를 개발하였다. 유전층의 전기비저항과 유전상수 값은 HTESC가 적합하게 작동하기에 필요한 요구조건을 만족하였으며, 하부절연층재료와 열팽창계수가 유사하여 구조적인 안정성이 확보되었다. 유전층과 절연 층간의 접합층 재료로는 입자오염 문제의 최소화를 위해 붕규산염 유리재료를 선택하였고, 전극재료로는 은을 사용하였다. 상부유전 층과 하부절연층 사이에서 붕규산염 유리는 안정되게 접합되었으며, 우려 되었던 은전극의 유전층이나 유리층과의 확산 및 반응이 관찰되지 않았다. 제조된 HTESC의 척킹(chucking)특성은 상용 HTESC에 비하여 우수하게 나타났다.

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중, 고압용 적층 세라믹 캐패시터 제작 및 분석 (Fabrication and Analysis of Multilayer Ceramic Capacitors for Medium and High Voltage)

  • 윤중락;김민기;이헌용;이석원
    • 한국전기전자재료학회논문지
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    • 제18권8호
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    • pp.685-689
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    • 2005
  • In the fabrication and design of MLCCs (Multilayer Ceramic Capacitors) with Ni inner electrode for medium and high voltage, reliability and dielectric breakdown mode have been investigated. For thickness of green sheet, the relationship between the rated voltage versus the thickness of green sheet. Increasing the thickness of green sheet increases the dielectric breakdown voltage. However, a practical limit to this linear relationship occurs at 30 urn and above. As the thickness of green sheet increased, dielectric breakdown voltage and weibull coefficient is increased, but abruptly decrease at 30 urn and 36 urn. When 24 urn of green sheet thickness, weibull coefficient and dielectric breakdown voltage were 13.58 and 70 V/um respectively. The results enabling the MLCCs to demonstrate high levels of reliability at medium and high voltage.

원자층 식각을 이용한 Sub-32 nm Metal Gate/High-k Dielectric CMOSFETs의 저손상 식각공정 개발에 관한 연구

  • 민경석;김찬규;김종규;염근영
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.463-463
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    • 2012
  • ITRS (international technology roadmap for semiconductors)에 따르면 MOS(metal-oxide-semiconductor)의 CD (critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/$SiO_2$를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두된다고 보고하고 있다. 일반적으로 high-k dielectric를 식각시 anisotropic 한 식각 형상을 형성시키기 위해서 plasma를 이용한 RIE (reactive ion etching)를 사용하고 있지만 PIDs (plasma induced damages)의 하나인 PIED (plasma induced edge damage)의 발생이 문제가 되고 있다. PIED의 원인으로 plasma의 direct interaction을 발생시켜 gate oxide의 edge에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 high-k dielectric의 식각공정에 HDP (high density plasma)의 ICP (inductively coupled plasma) source를 이용한 원자층 식각 장비를 사용하여 PIED를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. One-monolayer 식각을 위한 1 cycle의 원자층 식각은 총 4 steps으로 구성 되어 있다. 첫 번째 step은 Langmuir isotherm에 의하여 표면에 highly reactant atoms이나 molecules을 chemically adsorption을 시킨다. 두 번째 step은 purge 시킨다. 세 번째 step은 ion source를 이용하여 발생시킨 Ar low energetic beam으로 표면에 chemically adsorbed compounds를 desorption 시킨다. 네 번째 step은 purge 시킨다. 결과적으로 self limited 한 식각이 이루어짐을 볼 수 있었다. 실제 공정을 MOS의 high-k dielectric에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU (North Carolina State University) CVC model로 구한 EOT (equivalent oxide thickness)는 변화가 없으면서 mos parameter인 Ion/Ioff ratio의 증가를 볼 수 있었다. 그 원인으로 XPS (X-ray photoelectron spectroscopy)로 gate oxide의 atomic percentage의 분석 결과 식각 중 발생하는 gate oxide의 edge에 trap의 감소로 기인함을 확인할 수 있었다.

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