• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.155-158
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• 1988

The fabrication of devices using plans technology could lend to n serious degradation in the breakdown voltage as a result of high electric field at the edges. An elegant approach to reducing the electric field at the edge is by using field limiting ring. The presence of surface charge has n strong influrence on the depletion layer spreading at the surface region because this charge complements the charge due to the ionized acceptors inside the depletion layer. Surface charge of either polarity can lower the breakdown voltage because it affects the distribution of electric field st the edges. In this paper we discuss the influrences of fixed oxide charge on the breakdown voltage of the p+/n junction with field limiting ring(or without field limiting ring).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.78-88
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• 1994

The electrical properties of TiM/TiSi$_{2}$ bilayer formed by rapid thermal anneal in NH$_{3}$ ambient after the Ti film is deposited on silicon cubstrate are investigated. N$^{+}$ contact resistance slightly increases with increasing annealing temperature with P$^{+}$ contact resistance decreases. The contact resistance of N$^{+}$ contance was less than 24[.OMEGA.] but P$^{+}$ thatn that of N$^{+}$ contact but the leakage current indicates degradation of the contact at high annealing temperature for both N$^{+}$ and contacts. The leakage current of N$^{+}$ Junction was less than 0.06[fA/${\mu}m^{2}$] but P$^{+}$ contact was 0.11-0.15[fA/${\mu}m^{2}$]. The junction breakdown voltage for N$^{+}$ junction remains contant with increasing annealing temperature while P$^{+}$ junction slightly decreases. The Electrical properties of a two step annealing are better than that of one step annealing. The Tin/TiSi$_{2}$ bilayer formed by RTA in NH$_{3}$ ambient reveals good electrical properties to be applicable at ULSI contact.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.14-21
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• 2004

It is essential to increase the switching speed of power devices to reduce the energy loss because high frequency is commonly used in power device operation these days. In this work electron irradiation has been conducted to reduce the lifetime of minority carriers and thereby to increase the switching speed of a$p^+- n^-$ junction diode. Effects of electron irradiation on the electrical properties of the diode are reported The switching speed is effectively increased. Also the junction leakages and the forward voltage drop which are anticipated to increase are found to be negligible in the $p^+- n^-$ junction diodes irradiated with the optimum energy and dose. The analysis results of DLTS and C-V profiling indicate that the defects induced by electron irradiation in the silicon substrate are donor-like ones which have the energy levels of 0.284 eV and 0.483 eV. Considering all the experimental results in this study, it might be concluded that electron irradiation is a very useful technique in improving the switching speed and thereby reducing the energy loss of $p^+- n^-$ junction diode power devices.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1072-1074
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• 1995

Zinc-Borosilicate is used as a side insulastor wall to make high breakdown voltage with one Field Limiting Ring in a p-n junction. It is known that surface charge can be yield at the interface of Zinc-Borosilicate Glass/Silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage improved more than 660V without using more FLR.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.62-70
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• 1984

N+NPP+ HLEBSF (high low emitter back surface field) solar cells which have N+N high low junction in the emitter as well as N+PP+ BSF cells were designed and fabricated by using <111> oriented P type Si wafers with the resistivity of 10$\Omega$/$\textrm{cm}^2$ and the thickness of 13-15 mil. Physical parameters (impurity concentration, thickness) at each region of N+PP+ and N+NPP+ cell were made equally through same masks and simultaneous process except N region of HLEBSF cell to investigate the high low emitter junction effect for efficiency improvement. Under the light intensity of 100 mW/$\textrm{cm}^2$, total area (active area) conversion efficiency were typically 10.94% (12.16%) for N+PP+ BSF cells and 12.07% (13.41%) for N+N PP+ cells. Efficiency improvement of N+NPP+ cell which has high low emitter Junction structure is resulted from the suppression of emitter recombination current and the increasement of open circuit voltage (Voc) and short circuit current (Ish) by removing heavy doping effects occurring in N+ emitter region.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.257.2-257.2
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• 2015

In this paper, we report on the 10.33% efficient thin film/bulk tandem solar cells with the top cell made of amorphous silicon thin film and p-type bulk crystalline silicon bottom cell. The tunneling junction layers were used the doped nanocrystalline Si layers. It has to allow an ohmic and low resistive connection. For player and n-layer, crystalline volume fraction is ~86%, ~88% and dark conductivity is $3.28{\times}10-2S/cm$, $3.03{\times}10-1S/cm$, respectively. Optimization of the tunneling junction results in fill factor of 66.16 % and open circuit voltage of 1.39 V. The open circuit voltage was closed to the sum of those of the sub-cells. This tandem structure could enable the effective development of a new concept of high-efficiency and low cost cells.

• Journal of Satellite, Information and Communications
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• v.9 no.3
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• pp.15-21
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• 2014

An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), was analyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source (CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapback holding voltage and on-resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.396-399
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• 2003

4H-SiC un diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base region and p+ region in the n-epilayer. We have obtained up to 1782V of reverse breakdown voltage in the un diode with two FLRs on loom thick epilayer. The differential on-resistances of the fabricated diode are $5.3m{\Omega}cm^2$ at $100A/cm^2$ and $2.7m{\Omega}cm^2$ at $1kA/cm^2$, respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than that of diode without an FLR. Regardless of the activation temperature, the un diode with a FLR located 5um apart from main junction has the highest mean breakdown voltage around 1600V among the diodes with one ring. On the other hand, the pn diode with two rings showed different behavior with activation temperature. It reveals that high voltage SiC pn diodes with low on-resistance can be fabricated by using the FLR edge termination.