• Title/Summary/Keyword: High voltage p-n junction

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Realistic Simulations on Reverse Junction Characteristics of SiC and GaN Power Semiconductor Devices

  • Wei, Guannan;Liang, Yung C.;Samudra, Ganesh S.
    • Journal of Power Electronics
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    • v.12 no.1
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    • pp.19-23
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    • 2012
  • This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.

Physics and current density-voltage characteristics of $a-Si_{1-x}Ge_x:H$ alloy p-i-n solar cells ($a-Si_{1-x}Ge_x:H$ 화합물(化合物) p-i-n 태양전지(太陽電池)의 물리(物理) 및 전류밀도(電流密度)-전압(電壓) 특성(特性))

  • Kwon, Young-Shik
    • Proceedings of the KIEE Conference
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    • 1994.07b
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    • pp.1435-1438
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    • 1994
  • The effects of Ge composition variation in $a-Si_{1-x}Ge_x:H$ alloy p-i-n solar cells on the physical properties and current density-voltage characteristics are analyzed by a new simulation modelling based on the update published experimental datas. The simulation modelling includes newly formulated density of gap density spectrum corresponding to Ge composition variation and utilizes the newly derived generation rate formulars which include the reflection coefficients and can apply to multijunction structures as well as single junction structure. The effects in $a-Si_{1-x}Ge_x:H$ single junction are analyzed through the efficiency, fill factor, open circuit voltage, short circuit current density, free carriers, trap carriers, electric field, generation rate and recombination rate. Based on the results analyzed in single junction structure, the applications to multiple junction structures are discussed and the optimal conditions reaching to a high performance are investigated.

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Junction termination technology for 4H-SiC devices (Junction termination 기법에 따른 4H-SiC 소자의 항복전압 특성 분석)

  • Kim, H.Y.;Bahng, W.;Song, G.H.;Kim, N.K.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.286-289
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    • 2003
  • In the case of high voltage devices, junction termination plays an important role in determining the breakdown voltage of the device. The mesa junction termination has been demonstrated to yield nearly ideal breakdown voltage for 6H-SiC p-n junctions. However, such an approach may not be attractive because of the nonplanar surface, which is difficult to passivate. Moreover, In case of 4H-SiC, ideal breakdown voltage could not be achieved using mesa junction termination. For 4H-SiC planar junction termination technique is more useful one rather than mesa junction termination. In this paper, breakdown characteristics of the 4H-SiC device with planar junction termination, such as FLR(Field Limiting Ring), FP(Field Plate) and JTE(Junction Termination Extension), is presented. In the case of the FLR, breakdown voltage of 1800V is obtained. And breakdown voltage of 1000V and 1150V is also obtained for the case of FP and JTE case, respectively.

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Super Junction LDMOS with N-Buffer Layer (N 버퍽층을 갖는 수퍼접합 LDMOS)

  • Park Il-Yong
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.55 no.2
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    • pp.72-75
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    • 2006
  • A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

Electrical Properties of Single Crystal CdTe by Impurity (불순물에 의한 CdTe단결정의 전기적 특성)

  • 박창엽
    • 전기의세계
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    • v.20 no.2
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    • pp.9-14
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    • 1971
  • N type single crystal CdTe is grown by doping Gallium as 0.01 percent, by using zone melting method. And also p type CdTe is grown by doping Ag, Sb, and Te as 0.01%. Resistivity and Concentration of the n.p type single crystal are measured. And then Li ions are implanted on the n type CdTe by high voltage accellerator with different amount of impurity. Indium is evaporated on the p type in high vacuum condition. These sample are heated so as to make P-N Junction in Argon gas flow. Electrical properties for solar cell are investigated. Photovoltage and current are found to be varyed according to following factor: 1) amount of impurity 2) diffusion thickness 3) temperature and time for making P-N junction. Efficiency of the P-N Junction evaporated Indium is 6.5 when it is heated at 380.deg. C for 15 minutie.

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Analysis of Electrical Characteristics According to the Pillar Spacing of 4.5 kV Super Junction IGBT (4.5 kV급 Super Junction IGBT의 Pillar 간격에 따른 전기적 특성 분석)

  • Lee, Geon Hee;Ahn, Byoung Sup;Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.33 no.3
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    • pp.173-176
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    • 2020
  • This study focuses on a pillar in which is implanted a P-type maneuver under a P base. This structure is called a super junction structure. By inserting the pillar, the electric field concentrated on the P base is shared by the pillar, so the columns can be dispersed while maintaining a high breakdown voltage. Ten pillars were generated during the multi epitaxial process. The interval between pillars is varied to optimize the electric field to be concentrated on the pillar at a threshold voltage of 6 V, a yield voltage of 4,500 V, and an on-state voltage drop of 3.8 V. The density of the filler gradually decreased when the interval was extended by implanting a filler with the same density. The results confirmed that the size of the depletion layer between the filler and the N-epitaxy layer was reduced, and the current flowing along the N-epitaxy layer was increased. As the interval between the fillers decreased, the cost of the epitaxial process also decreased. However, it is possible to confirm the trade-off relationship that deteriorated the electrical characteristics and efficiency.

A study on the breakdown characteristics of power p-n junction device using field limiting ring and side insulator wall (전계제한테와 측면 유리 절연막 사용한 전력용 p-n 접합 소자의 항복 특성 연구)

  • 허창수;추은상
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.45 no.3
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    • pp.386-392
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    • 1996
  • Zinc-Borosilicate is used as a side insulator wall to make high breakdown voltage with one Field Limiting Ring in a power p-n junction device in simulation. It is known that surface charge density can be yield at the interface of Zinc-Borosilicate glass / silicon system. When the glass is used as a side insulator wall, surface charge varied potential distribution and breakdown voltage is improved 1090 V under the same structure.The breakdown voltage under varying the surface charge density has a limit value. When the epitaxial thickness is varied, the position of FLR doesn't influence to the breakdown characteristic not only under non punch-through structure but also under punch-through structure. (author). 7 refs., 12 figs., 2 tabs.

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Fabrication and Characteristics of a Varactor Diode for UHF TV Tuner Operated within Low Tuning Voltage (저전압 UHF TV 튜너용 바렉터 다이오드의 제작 및 특성)

  • Kim, Hyun-Sik;Moon, Young-Soon;Son, Won-Ho;Choi, Sie-Young
    • Journal of Sensor Science and Technology
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    • v.23 no.3
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    • pp.185-191
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    • 2014
  • The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

An Analysis on Optimal Design and Electrical Characteristics of CT-IGBT(Circular Trench IGBT) (CT-IGBT의 최적 설계 및 전기적 특성에 관한 분석)

  • Kwak, Sang-Hyeon;Seo, Jun-Ho;Seo, In-Kon;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.22-23
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    • 2008
  • The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the Breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from p base and n drift junction to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction change of current path which pass through reversed layer channel.

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An Analysis of IGBT(Insulator Gate Bipolar Transistor) Structure with an Additional Circular Trench Gate using Wet Oxidation (습식 산화를 이용한 원형 트렌치 게이트 IGBT에 관한 연구)

  • Kwak, Sang-Hyeon;Kyoung, Sin-Su;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.11
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    • pp.981-986
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    • 2008
  • The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from the junction of between p base and n drift to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction changed of current path which pass through reversed layer channel. The electrical characteristics were studied by MEDICI simulation results.