• 한국전기전자재료학회논문지
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• 제24권5호
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.

• ETRI Journal
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• 제37권5호
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• pp.906-916
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• 2015

High-speed I/O channels require adaptive techniques to optimize the settings for filter tap weights at decision feedback equalization (DFE) read channels to compensate for channel inter-symbol interference (ISI) and crosstalk from multiple adjacent channels. Both ISI and crosstalk tend to vary with channel length, process, and temperature variations. Individually optimizing parameters such as those just mentioned leads to suboptimal solutions. We propose a joint optimization technique for crosstalk cancellation (XTC) at DFE to compensate for both ISI and XTC in high-speed I/O channels. The technique is used to compensate for between 15.7 dB and 19.7 dB of channel loss combined with a variety of crosstalk strengths from $60mV_{p-p}$ to $180mV_{p-p}$ adaptively, where the transmit non-return-to-zero signal amplitude is a constant $500mV_{p-p}$.

• 한국전기전자재료학회논문지
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• 제24권6호
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.352-352
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• 2010

Silicon Carbide (SiC) power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this paper, we report the effect of the P-base doping concentration ($N_{PBASE}$) on the transient characteristics of 4H-SiC DMOSFETs. By reducing $N_{PBASE}$, switching time also decreases, primarily due to the lowered channel resistance. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimization of superior switching performance.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2006년도 춘계학술대회 논문집
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• pp.119-122
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• 2006

In this study, bottom-up type powder processing and top-down type SPD (severe plastic deformation) approaches were combined in order to achieve full density of 1 vol.% carbon nanotube (CNT)-metal matrix composites with superior mechanical properties by improved particle bonding and least grain growth, which were considered as a bottle neck of the bottom-up method using the conventional powder metallurgy of compaction and sintering. ECAP (equal channel angular pressing), the most promising method in SPD, was used for the CNT-Cu powder consolidation. The powder ECAP processing with 1, 2, 4 and 8 route C passes was conducted at room temperature. It was found by mechanical testing of the consolidated 1 vol.% CNT-Cu that high mechanical strength could be achieved effectively as a result of the Cu matrix strengthening and improved particle bonding during ECAP. The ECAP processing of powders is a viable method to achieve fully density CNT-Cu nanocomposites.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• 한국전자통신학회논문지
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• 제9권3호
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• pp.279-284
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• 2014

본 논문에서는 p-채널 저온 다결정 실리콘 박막 트랜지스터의 문턱전압 변동을 보상할 수 있는 새로운 OLED 화소회로를 제안하였다. 제안한 5-TFT OLED 화소회로는 4개의 스위칭 박막 트랜지스터, 1개의 OLED 구동 박막 트랜지스터 및 1개의 정전용량으로 구성되어 있다. 제안한 화소회로의 한 프레임은 초기화 구간, 문턱전압 감지 및 데이터 기입 구간, 데이터 유지 구간 및 발광 구간으로 나누어진다. SmartSpice 시뮬레이션 결과, 구동 트랜지스터의 문턱전압이 ${\pm}0.25V$ 변동 시 최대 OLED 전류의 오차율은 -4.06%이였고 구동 트랜지스터의 문턱전압이 ${\pm}0.50V$ 변동 시 최대 OLED 전류의 오차율은 9.74%였다. 따라서 제안한 5T1C 화소회로는 p-채널 다결정 실리콘 박막 트랜지스터의 문턱전압 변동에 둔감하여 균일한 OLED 전류를 공급함을 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.387.1-387.1
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• 2014

A new class of temperature-sensing materials is demonstrated along with their integration into transparent and flexible field-effect transistor (FET) temperature sensors with high thermal responsivity, stability, and reproducibility. The novelty of this particular type of temperature sensor is the incorporation of an R-GO/P(VDF-TrFE) nanocomposite channel as a sensing layer that is highly responsive to temperature, and is optically transparent and mechanically flexible. Furthermore, the nanocomposite sensing layer is easily coated onto flexible substrates for the fabrication of transparent and flexible FETs using a simple spin-coating method. The transparent and flexible nanocomposite FETs are capable of detecting an extremely small temperature change as small as $0.1^{\circ}C$ and are highly responsive to human body temperature. Temperature responsivity and optical transmittance of transparent nanocomposite FETs were adjustable and tuneable by changing the thickness and R-GO concentration of the nanocomposite.

• 대한전자공학회논문지SD
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• 제46권4호
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• pp.21-27
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• 2009

본 연구에서는 고온에서 Schottky barrier SOI nMOS 및 pMOS의 전류-전압 특성을 분석하기 위해서 Er 실리사이드를 갖는 SB-SOI nMOSFET와 Pt 실리사이드를 갖는 SB-SOI pMOSFET를 제작하였다. 게이트 전압에 따른 SB-SOI nMOS 및 pMOS의 주된 전류 전도 메카니즘을 온도에 따른 드레인 전류 측정 결과를 이용하여 설명하였다. 낮은 게이트 전압에서는 온도에 따라 열전자 방출 및 터널링 전류가 증가하므로 드레인 전류가 증가하고 높은 게이트 전압에서는 드리프트 전류가 감소하여 드레인 전류가 감소하였다. 고온에서 ON 전류가 증가하지만 드레인으로부터 채널영역으로의 터널링 전류 증가로 OFF 전류가 더 많이 증가하게 되므로 ON/OFF 전류비는 감소함을 알 수 있었다. 그리고 SOI 소자나 bulk MOSFET 소자에 비해 SB-SOI nMOS 및 pMOS의 온도에 따른 문턱전압 변화는 작았고 subthreshold swing은 증가하였다.