• Journal of the Korean Society of Propulsion Engineers
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• v.2 no.3
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• pp.99-106
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• 1998

The performance of the turbofan engine, a medium scale civil aircraft which has been developing in Rep. of Korea, was analyzed and the control scheme for optimization the performance was studied. The dynamic and real-time linear simulation was performed in the previous study The result was that the fuel scedule of the step increase overshoot the limit temperature(3105 $^{\cire}R$) of the high pressure turbine and got small surge margine of the high pressure compressor. Therefore a control scheme such as the LQR(Linear Quadratic Regulator) was applied to optimizing the performance in this studies. The linear model was expected for designing controller and the real time linear model was developed to be closed to nonlinear simulation results. The system matrices were derived from sampling operating points in the scheduled range and then the least square method was applied to the interpolation between these sampling points, where each element of matrices was a function of the rotor speed. The control variables were the fuel flow and the low pressure compressor bleed air. The controlled linear model eliminated the inlet temperature overshoot of the high pressure turbine and obtained maximum surge margins within 0.55. The SFC was stabilized in the range of 0.355 to 0.43.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

• Environmental Engineering Research
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• v.24 no.1
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• pp.159-172
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• 2019

To investigate the influence of pollution events on the chemical composition and formation processes of aerosol particles, 24-h integrated size-segregated particulate matter (PM) was collected during the fall season at an urban site of Gwangju, Korea and was used to determine the concentrations of mass, water-soluble organic carbon (WSOC) and ionic species. Furthermore, black carbon (BC) concentrations were observed with an aethalometer. The entire sampling period was classified into four periods, i.e., typical, pollution event I, pollution event II, and an Asian dust event. Stable meteorological conditions (e.g., low wind speed, high surface pressure, and high relative humidity) observed during the two pollution events led to accumulation of aerosol particles and increased formation of secondary organic and inorganic aerosol species, thus causing $PM_{2.5}$ increase. Furthermore, these stable conditions resulted in the predominant condensation or droplet mode size distributions of PM, WSOC, $NO_3{^-}$, and $SO{_4}^{2-}$. However, difference in the accumulation mode size distributions of secondary water-soluble species between pollution events I and II could be attributed to the difference in transport pathways of air masses from high-pollution regions and the formation processes for the secondary chemical species. The average absorption ${\AA}ngstr{\ddot{o}}m$ exponent ($AAE_{370-950}$) for 370-950 nm wavelengths > 1.0 indicates that the BC particles from traffic emissions were likely mixed with light absorbing brown carbon (BrC) from biomass burning (BB) emissions. It was found that light absorption by BrC in the near UV range was affected by both secondary organic aerosol and BB emissions. Overall, the pollution events observed during fall at the study site can be due to the synergy of unfavorable meteorological conditions, enhanced secondary formation, local emissions, and long-range transportation of air masses from upwind polluted areas.

• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.121-128
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• 2003

Acoustic Echo Cancellation(m) is very active research topic having many applications like teleconference and hands-free communication and it employs Double Talk Detector(DTD) to indicate whether the near-end speaker is active or not. However. the DTD is very sensitive to the variation of acoustical environment and it sometimes provides wrong information about the near-end speaker. In this paper, we are focusing on the development of robust DTD algorithm which is a basic building block for reliable AEC system. The proposed AEC system consists of delayless subband AEC and narrow-band DTD. Delayless subband AEC has proven to have excellent performance of echo cancellation with a low complexity and high convergence speed. In addition, it solves the signal delay problem in the existing subband AEC. On the other hand, the proposed narrowband DTD is operating on low frequency subband. It can take most advantages from the narrow subband such as a low computational complexity due to the down-sampling and the reliable DTD decision making procedure because of the low-frequency nature of the subband signal. From the simulation results of the proposed narrowband DTD and wideband DTD, we confirm that the proposed DTD outperforms the wideband DTD in a sense of removing possible false decision making about the near-end speaker activity.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Journal of the Korea institute for structural maintenance and inspection
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• v.27 no.2
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• pp.17-24
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• 2023

A post-processing technique for the measurement signal of a solenoid-type sensor is introduced. The solenoid-type sensor nondestructively evaluates an external tendon of prestressed concrete using the total flux leakage (TFL) method. The TFL solenoid sensor consists of primary and secondary coils. AC electricity, with the shape of a sinusoidal function, is input in the primary coil. The signal proportional to the differential of the input is induced in the secondary coil. Because the amplitude of the induced signal is proportional to the cross-sectional area of the tendon, sectional loss of the tendon caused by ruptures or corrosion can be identified by the induced signal. Therefore, it is important to extract amplitude information from the measurement signal of the TFL sensor. Previously, the amplitude was extracted using local maxima, which is the simplest way to obtain amplitude information. However, because the sampling rate is dramatically decreased by amplitude extraction using the local maxima, the previous method places many restrictions on the direction of TFL sensor development, such as applying additional signal processing and/or artificial intelligence. Meanwhile, the proposed method uses amplitude demodulation to obtain the signal amplitude from the TFL sensor, and the sampling rate of the amplitude information is same to the raw TFL sensor data. The proposed method using amplitude demodulation provides ample freedom for development by eliminating restrictions on the first coil input frequency of the TFL sensor and the speed of applying the sensor to external tension. It also maintains a high measurement sampling rate, providing advantages for utilizing additional signal processing or artificial intelligence. The proposed method was validated through experiments, and the advantages were verified through comparison with the previous method. For example, in this study the amplitudes extracted by amplitude demodulation provided a sampling rate 100 times greater than those of the previous method. There may be differences depending on the given situation and specific equipment settings; however, in most cases, extracting amplitude information using amplitude demodulation yields more satisfactory results than previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• Journal of the Korea Computer Graphics Society
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• v.23 no.1
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• pp.25-32
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• 2017

This paper proposes a novel acceleration method for particle based large scale fluid simulation. Traditional particle-based fluid simulation has been implemented by interacting with physical quantities of neighbor particles through the Smoothed Particle Hydrodynamics(SPH) technique[1]. SPH method has the characteristic that there is no visible change compared to the computation amount in a part where the particle movement is small, such as a calm surface or inter-fluid. This becomes more prominent as the number of particles increases. Previous work has attempted to reduce the amount of spare computation by adaptively dividing each part of the fluid. In this paper, we propose a technique to calculate the motion of the entire particles by using the physical quantities of the near sampled particles by sampling the particles inside the fluid at regular intervals and using them as reference points of the fluid motion. We propose a technique to adaptively generate a triangle map based on the position of the sampled particles in order to efficiently search for nearby particles, and we have been able to interpolate the physical quantities of particles using the barycentric coordinate system. The proposed acceleration technique does not perform any additional correction for two classes of fluid particles. Our technique shows a large improvement in speed as the number of particles increases. The proposed technique also does not interfere with the fine movement of the fluid surface particles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2164-2170
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• 2010

Digital Radio Frequency Memory, ( as DRFM ), is a device with the ability to restore output to the input RF signal in the required time after storing the incoming RF signals. Therefore DRFM is widely used in Jammer, EW Simulator, Target Echo Generator, and so on. This paper proposes its hardware implementation composed with the high frequency part and the digital processing part consisting of RF input/output module and local oscillator module. It is also proposed the replicated signal generation method which is consisted of the Analog-Digital conversion in the form of pulsed RF signal quantization, and FPGA to save and produce the playback signal, and RF signals to produce a Digital-Analog Conversion in the digital processing unit. This proposed scheme applied to test board and confirmed the validity of the proposed scheme through the test results obtained by the simulated input signals.