• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.193-199
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• 1995

A novel imaging method in which time-division spinning reticle samples different pixel location of input image in different time is presented. The lens collects the beam passing throughthe reticle to a photodetector. Image reconstruction is accomplished by sampling the detector output corresponding to the spinning speed of reticle. Since the time-division reticle system removed the necessity of bandpass filter bank which has sharp cut-off characteristic, high resolution image is obtained without increasing the number of filter. To confirm the validity of this method, a computer simulation and an optical experiment using visual light are presented.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.248-253
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• 1992

In the development of a high speed and light weight manipulator, it is necessary to consider the structural elasticity of a robotic arm. The analysis of the infinite mode dynamic of robotic arm must be performed to obtain the finite mode modelling to achieve the feasible controller design of the robotic arm. The modelling procedure of the robotic arm is also illustrated. The controlled mode of the modelled dynamic can be derived by truncating the higher vibrational mode to result in the low order system for the sampling in the control signal is confined to the higher mode. And it is controlled by the pole assignment which can compensate the unmodelled dynamic effects. The unmodelled dynamic can result in the instability of the controlled system, which is known as spillover. The controller design of the low order system is simulated by the pole assignment and optimal control theory.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.263-266
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.97-100
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• 2000

The most important technology is the compression methods in the multimedia society. Audio files are rapidly propagated through internet. MP-3(MPEG-1 Layer3) is offered to CD tone quality in 128kbps, but 64kbps below tone-quality is abruptly down. On the other hand, MPEG-II AAC (Advanced Audio Coding) is not compatible with MPEG-I, but AAC has a high compression ratio 1.4 times better than MP-3 and it has max. 7.1 channel and 96KHz sampling rate. In this paper, we designed the optimized MDCT (Modified Discrete Cosine Transform) that could decrease the capacity of enormous computation and could increase the processing speed in the MPEG-2 AAC encoder.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.7
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• pp.669-674
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• 2011

In this paper, a method for reduction of spurious signal in Digital RF Memory(DRFM) is proposed. Spurious response is a major performance issue of DRFM. This method is based on mixing a random phase LO signal into input IF signal and sampling it. The random phase LO signal is generated by high speed phase shifting characteristic of Direct Digital Synthesizer(DDS). Through this technique, we achieved an enhancement of 5~10 dB of spurious response.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.667-670
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• 2003

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position, because the position of rotor is an essential information. In the high-speed region, switching angles are fluctuated back and forth out of\ the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.511-513
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• 2004

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position, because the position of rotor is an essential information. In the high-speed region, switching angles are fluctuated back and forth out of the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.18 no.12
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• pp.1229-1236
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• 2008

A set of modal parameters of a stay-cable have been extracted fi:on a moving picture captured by a digital camera supported by shaking hands. It is hard to identify the center of targets attached on the cable surface from the blurred cable motion image, because of the high speed motion of cable, low sampling frequency of camera, and the shaking effect of camera. This study proposes a multi-template matching algorithm to resolve such difficulties. In addition, a sensitivity-based system identification algorithm is introduced to extract the natural frequencies and damping ratios from the ambient cable vibration data. Three sets of vibration tests are conducted to examine the validity of the proposed algorithms. The results show that the proposed technique is pretty feasible for extracting modal parameters from the severely shaking motion pictures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.