• 대한전자공학회논문지SD
• /
• 제46권10호
• /
• pp.70-78
• /
• 2009

본 논문에서는 고속 저전압 차동 신호(Low-Voltage Differential Signaling, LVDS) 전송방식의 응용을 위한 전송선 분석 및 설계 최적화 방법을 제안한다. 차동 전송 경로 및 저전압 스윙 방법의 발전으로 인해 저전압 차동 신호 전송방식은 데이터 통신 분야, 고 해상도 디스플레이 분야, 평판 디스플레이 분야에서 매우 적은 소비전력, 개선된 잡음 특성 및 고속 데이터 전송률을 제공한다. 본 논문은 차동 유연성 인쇄 회로 보드(flexible printed circuit board, FPCB) 전송선에서 선 폭, 선 두께 및 선간격과 같은 전송선 설계 변수들의 최적화 기법을 이용하여 직렬 접속된 전송선에서 발생하는 임피던스 부정합과 신호 왜곡을 감소시키기 위해 개선 모델과 개발된 수식을 제안한다. 이러한 차동 FPCB 전송선의 고주파 특성을 평가하기 위해 주파수 영역에서 전파(full-wave) 전자기 시뮬레이션 및 시간 영역 시뮬레이션을 각각 수행하였다. 본 논문에서 제안하는 방법은 저전압 차동 신호 방식의 응용을 위한 고속 차동 FPCB 전송선을 최적화하는데 매우 도움이 되리라 믿는다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.975-978
• /
• 1999

The transmission line effects of IC interconnects have a substantial effect on a hish-speed VLSI circuit performance. The effective transmission lime parameters are changed with the increase of the operation frequency because of the skin of the skin effect, proximity effect, and silicon substrate. A new signal delay estimation methodology based on the RLC-distributed circuit model is presented ［2］. The methodology is demonstrated by using SPICE simulation and a high-frequency experiment technique.

• 한국전자파학회지:전자파기술
• /
• 제24권2호
• /
• pp.35-50
• /
• 2013

This paper discusses effects of mesh planes on signal integrity in high-speed glass ceramic packages. One of serious signal integrity issues in high-speed glass ceramic packages is high far-end (FE) noise coupling between signal interconnects. Based on signal integrity analysis, a methodology is presented for reducing far-end noise coupling between signal interconnects in high-speed glass ceramic modules. This methodology employing power/ground mesh planes with alternating spacing and a via-connected coplanar-type shield (VCS) structure is suggested to minimize far-end noise coupling between signal lines in high-speed glass ceramic packages. Optimized interconnect structure based on this methodology has demonstrated that the saturated far-end noise coupling of a typical interconnect structure in glass ceramic modules could be reduced significantly by 73.3 %.

• Journal of Electrical Engineering and Technology
• /
• 제11권1호
• /
• pp.175-183
• /
• 2016

This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of −40dB in Near-End Crosstalk (NEXT) and −60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.

• Journal of electromagnetic engineering and science
• /
• 제11권1호
• /
• pp.62-69
• /
• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• ETRI Journal
• /
• 제45권5호
• /
• pp.910-921
• /
• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• 전자통신동향분석
• /
• 제39권5호
• /
• pp.98-107
• /
• 2024

Applications such as artificial intelligence continue to grow in complexity and scale. Thus, the demand for scalable computing is increasing for achieving faster data processing and improved efficiency. This requirement has led to the development of memory-centric computing and high-speed fabric interconnection technologies. Memory-centric computing reduces the latency and enhances the system performance by shifting the focus from the central processing unit to the memory, whereas high-speed fabric interconnects enable efficient data transfer across various computing resources. Technologies such as Gen-Z, OpenCAPI, and CCIX have been integrated into the CXL (Compute Express Link) standard since 2019 to improve communication and cache coherence. Ethernet-based interconnects such as RoCE, InfiniBand, and OmniXtend also play a crucial role in providing high-speed data transfer and low latency. We explore the latest trends and prospects of these technologies, highlighting their benefits and applications.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2007년도 추계종합학술대회
• /
• pp.761-764
• /
• 2007

본 논문은 저전압 차동 신호 방식 (Low-Voltage Differential Signaling, LVDS)의 응용을 위한 차동 전송 접속 경로의 분석 및 설계 최적화 방법을 제안한다. 차동 전송 경로 및 저전압 스윙 방법의 발전으로 인해 LVDS 방식은 데이터 통신 분야, 고 해상도 디스플레이 분야, 평판 디스플레이 분야에서 매우 적은 소비전력, 개선된 잡음 특성 및 고속 데이터 전송률을 제공한다. 본 논문은 차동 flexible printed circuit board (FPCB) 전송선에서 선 폭, 선 두께 및 선 간격과 같은 전송선 설계 변수들의 최적화 기법을 이용하여 직렬 접속된 전송선들에서 발생하는 임피던스 부정합과 신호 왜곡을 감소시키기 위해 개선 모델과 새로이 개발된 수식을 제안한다. 이러한 차동 FPCB 전송선의 고주파 특성을 평가하기 위해 주파수 영역에서 full-wave 전자기 시뮬레이션, 시간 영역 시뮬레이션 및 S 파라미터 시뮬레이션을 각각 수행하였다.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
• /
• pp.97.1-97
• /
• 1998

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.149-153
• /
• 1999

As VLSI technology advances rapidly, the operating frequency of digital systems becomes very fast. In such a high-speed system, there are many factors that threaten signal integrity. The noise sources in digital system include the noises in power supply, ground bounce and packaging media and distortions on single and multiple transmission lines. This paper will present a technology survey useful in the design of Gigabit interconnection systems. Some case studies have been constructed which show the lossy transmission line effect of skin effect. dielectric loss, with backplane connectors using the theoretical and practical conditions.