• Proceedings of the KIPE Conference
• /
• 2019.11a
• /
• pp.4-6
• /
• 2019

본 논문은 Modular Scalable Inverter System에서 큰 부피를 차지하는 인덕터를 저감하기 위한 방법을 제안한다. 최근 전력분야에서는 모듈형 전력변환 시스템을 사용함으로써 다양한 시스템에 필요한 전력을 공급하여 효율을 증가시키고 신뢰성을 높이는 방법들이 대두되고 있다. 하지만 모듈을 병렬로 사용하는 경우에는 모듈 간에 흐르는 순환 전류가 발생하게 된다. 이런 순환전류는 부하로 전력을 공급하지 않기 때문에 시스템 효율을 떨어트리고 전류제어 및 부하 분담을 방해한다. 따라서 병렬형 인버터에는 출력에 순환전류 저감을 위한 인덕터를 사용해야 한다는 단점이 있다. 모듈형 전력변환 장치에서 큰 크기의 출력 인덕터는 시스템 사이즈를 늘리고 비용을 증가시키고 전력밀도가 낮아지게 된다. 따라서 GaN HEMT (Gallium Nitride High Electron Mobility Transistor) 기반 인버터와 순환전류 저감 알고리즘을 사용하여 고속 스위칭을 함으로써 동일한 순환전류 저감 성능을 확보하지만 출력 인덕터의 크기를 줄이는 방안을 제시한다.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.6
• /
• pp.451-458
• /
• 2020

In this study, a trade-off analysis of a power conversion system (PCS) is performed in accordance with a power semiconductor device to establish the suitable operating frequency range for the anyplace induction heating system. A resonant network is designed under each operating frequency condition to compare and analyze the PCS losses depending on the power semiconductor device. On the basis of the simulation results, the PCS losses and frequency condition are calculated. The calculated results are then used for a trade-off analysis between Si-MOSFET and GaN-HEMT based on PCS. The suitable operating frequency range is determined, and the validity of the analysis results is verified by the experiment results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.11
• /
• pp.1064-1073
• /
• 2013

In this paper, a compact 370 W high efficiency GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) power amplifier(PA) using internal harmonic manipulation circuits is presented for cellular and L-band. We employed a new circuit topology for simultaneous high efficiency matching at both fundamental and 2nd harmonic frequency. In order to minimize package size, new 41.8 mm GaN HEMT and two MOS(Metal Oxide Semiconductor) capacitors are internally matched and combined package size $10.16{\times}10.16{\times}1.5Tmm^3$ through package material changes and wire bonded in a new package to improve thermal resistance. When drain biased at 48 V, the developed GaN HEMT power amplifier has achieved over 80 % Drain Efficiency(DE) from 770~870 MHz and 75 % DE at 1,805~1,880 MHz with 370 W peak output power(Psat.). This is the state-of-the-art efficiency and output power of GaN HEMT power amplifier at cellular and L-band to the best of our knowledge.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2000.02a
• /
• pp.186-186
• /
• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.242-242
• /
• 2012

Transparent oxide semiconductors are increasingly becoming one of good candidates for high efficient channel materials of thin film transistors (TFTs) in large-area display industries. Compare to the conventional hydrogenated amorphous silicon channel layers, solution processed ZnO-TFTs can be simply fabricated at low temperature by just using a spin coating method without vacuum deposition, thus providing low manufacturing cost. Furthermore, solution based oxide TFT exhibits excellent transparency and enables to apply flexible devices. For this reason, this process has been attracting much attention as one fabrication method for oxide channel layer in thin-film transistors (TFTs). But, poor electrical characteristic of these solution based oxide materials still remains one of issuable problems due to oxygen vacancy formed by breaking weak chemical bonds during fabrication. These electrical properties are expected due to the generation of a large number of conducting carriers, resulting in huge electron scattering effect. Therefore, we study a novel technique to effectively improve the electron mobility by applying environmental annealing treatments with various gases to the solution based Li-doped ZnO TFTs. This technique was systematically designed to vary a different lithium ratio in order to confirm the electrical tendency of Li-doped ZnO TFTs. The observations of Scanning Electron Microscopy, Atomic Force Microscopy, and X-ray Photoelectron Spectroscopy were performed to investigate structural properties and elemental composition of our samples. In addition, I-V characteristics were carried out by using Keithley 4,200-Semiconductor Characterization System (4,200-SCS) with 4-probe system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.180-180
• /
• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08a
• /
• pp.926-929
• /
• 2007

A significant progress has been made in the characterization of zinc oxide (ZnO) semiconductor as a new semiconductor layer instead of amorphous Si semiconductor used in thin film transistor due to its high electron mobility at low deposition temperature which is quite suitable for flexible display and OLED devices. The wet pattering of ZnO is another important issue with regard to mass production of ZnO thin film transistor device. However, the wet behavior of ZnO thin film in aqueous wet etching solutions conventionally used un TFT industry has not been reported yet, in this work, wet corrosion behavior of RF magnetron sputtered ZnO thin film in various wet solutions such as phosphoric and nitric acid solutions was studied using by electrochemical analysis. The effects of deposition parameters such as RF power and oxygen partial pressure on corrosion rate are also examined.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.114-121
• /
• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.4
• /
• pp.394-402
• /
• 2013

This paper presents design, fabrication and ruggedness test of switching-mode power amplifier using GaN(Gallium Nitride) HEMT(High Electron Mobility Transistor) for S-band radar applications. The power amplifier is designed to Class-F for high efficiency. The input signal for the measurement of the power amplifier is pulse signal at $100{\mu}s$ pulse width and duty cycle of 10 %. The measurement results of the fabricated Class-F power amplifier are a power gain of 10.8 dB, an output power of 40.8 dBm, a power added efficiency(PAE) of 54.2 %, and a drain efficiency of 62.6 %, at the center frequency. We proposed reliability test set-up of a power amplifier for ruggedness test. And we measured output power and efficiency according to VSWR(Voltage Standing Wave Ratio) variation. The designed power amplifier achieved output power of 32.6~41.1 dBm and drain efficiency of 23.4~63 % by changing VSWR, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.1-6
• /
• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.