• Convergence Security Journal
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• v.4 no.3
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• pp.19-25
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• 2004

This research develops an algorithm using image synthesis for a server to authenticate users and implements it. The server creates cards with random dots for users and distribute them to users. The server also manages information of the cards distributed to users. When there is an authentication request from a user, the server creates a server card based on information of the user' s card in real time and send it to the user. Different server card is generated for each authentication. Thus, the server card plays a role of one-time password challenge. The user overlaps his/her card with the server card and read an image(eg. a number with four digits) made up from them and inputs the image to the system. This is the authentication process. Keeping security level high, this paper proposes a technique to generate the image clearly and implements it.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.227-233
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• 2000

In this paper, we present a new high-level data path synthesis algorithm which solves the two design problems, namely, scheduling and allocation, with power minimization as a key design parameter. From the observations in previous works on data path synthesis for low power, we derive an integer programming (IP) formulation for the problem, from which we then develop an efficient heuristic to carry out the scheduling and allocation simultaneously. Our experimental results demonstrate that the proposed algorithm is very effective in saving power consumption of circuits significantly.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.4
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• pp.329-334
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• 2002

For the testability, this paper proposed the algorithm at autonomous synthesis which includes the data path structure as the self testing as possible on high level synthesis method when VHDL, coding is used in the system design area. In the proposed algorithm of this paper, MUXs and registers are assigned to the data path of designed system. And the designed data path could be mapped the H/W specification of described VHDL coding to the testable library. As a results, it was mapped H/W to the assign algorithm that is minimized MUX and the registers in collision graph.

• Journal of the Korean Physical Society
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• v.73 no.10
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• pp.1535-1540
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• 2018

In this study, we prepared and characterized Nb-doped $Li_7La_3Zr_{2-x}O_{12}$ (LLZNO) powder and pellets with a cubic garnet structure by using a modified sol-gel synthesis and hot pressing. LLZNO powder with a very small grain size and cubic structure without secondary phases could be obtained by using a synthesis method in which Li and La sources in a propanol solvent were mixed together with Zr and Nb sources in 2-methoxy ethanol. A pure cubic phase LLZNO pellet could be fabricated from the prepared LLZNO and an additional 6-wt% of $Li_2CO_3$ powder by hot pressing at $1050^{\circ}C$ and 15.8 MPa. The hot-pressed LLZNO pellet with a relative density of 99% exhibited a very dense surface morphology. The total Li ionic conductivity of the hot-pressed LLZNO was $7.4{\times}10^{-4}S/cm$ at room temperature, which is very high level compared to other reported values. The activation energy for ionic conduction was estimated to be 0.40 eV.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.803-806
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• 1998

This thesis proposes a new heuristic algorithm of integrated allocation and binding for high level synthesis. The proposed algorithm simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. This thesis shows the effectiveness of the algorithm by comparing the results of out experiments with those of existing system.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.75-78
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• 2000

This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp［1］high-level synthesis system.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.399-402
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• 2000

The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.302-305
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• 2000

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

• Journal of Microbiology and Biotechnology
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• v.10 no.5
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• pp.599-605
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• 2000

Lipopolysaccharide (LPS) is responsible for the tissue injury that occurs following the invasion of multicelluar organisms by Gram-negative microbes. The effect of LPS on IFN-$\gamma$-induced chemokine Mig gene expression in mouse peritoneal macrophages was investigated. Very little Mig mRNA was detectable upon exposure to LPS without IFN-$\gamma$. Although LPS alone is only minimally effective, LPS plus IFN-$\gamma$ synergized to produce a high level of Mig mRNA in the peritoneal macrophages. This synergy was not dependent on a new protein synthesis, and was not controlled at the level of the gene transcription. Futhermore, LPS did not increase IFN-$\gamma$-induced Mig mRNA stability. Accordingly, it is suggested the LPS may synergize the expression of IFN-$\gamma$-induced Mig mRNA through a process that depends on a pretranscriptional level or concurrent Mig mRNA translation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.5
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• pp.430-436
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• 2014

The mission objective of STEP Cube Lab. (Cube Laboratory for Space Technology Experimental Project) classified as a pico-class satellite is to verify the technical effectiveness of payloads such as variable emittance radiator, SMA washer, oscillating heat pipe and MEMS based solid propellant thruster researched at domestic universities. In addition, the MEMS concentrating photovoltaic power system and the non-explosive holding and separation mechanism with the advantages of high constraint force and low shock level will be developed as the primary payloads for on-orbit verification. In this study, the feasibility of the mission actualization has been confirmed by the preliminary system design.