• Title/Summary/Keyword: High Voltage Converter

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Implementation of Multiple Frequency Bioelectrical Impedance Analysis System for Body Composition Analysis (신체 성분 분석을 위한 다 주파수 생체전기 임피던스 분석 시스템 구현)

  • Kim, Seong-Cheol
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.11
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    • pp.5403-5408
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    • 2012
  • In this paper, we introduce the multiple frequency bio-electrical impedance analysis method for body composition analysis. And then we implement the multiple frequency bio-electrical impedance analysis system. Overall system consists of: multiple frequency alternating current signal generator contained alternating current signal, phase signal detector, voltage signal detector, micro controller, in-out device(key-pad LCD), conductivity electrodes, system power. We explain the architecture of the system and required theory to implement the system. In order to investigate the clinical significance of the body composition data, compare to the data measured by the expert body composition analyzer which provide high reproduction and precision. Finally, experimental results which are the correlation between the measured data show the very high reproduction performance of the body composition analysis in the proposed system.

Characteristic Analysis of Inductive Power Transfer System for PRT (소형궤도 열차용 유도 전력 전송 시스템 특성해석)

  • Min, Byung-Hun;Lee, Byung-Song
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.3
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    • pp.35-43
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    • 2007
  • In this paper, the inductive power collector using electromagnetic induction for vehicle such as the PRT(Personal Rapid Transit) system is suggested and son ideas for power collector design to improve tile power transfer performance are presented. And also, the analysis of the inductive power transfer system in conjunction with series resonant converter operating variable high frequency is shown. Of particular interest is the sensitivity of the complete system to variations in operational frequency and parameters. In inductive power transfer system electrical power is transferred from a primary winding in the form of a coil or tract to one or more isolated pick-up coils that my relative to the primary. The ability to transmit power without contact enables high reliability and easy maintenance that allows inductive power transfer system to be implemented in hostile environments. This technology has found application in many fields such as electric vehicles, PRT(Personal Rapid Transit) etc. But, low output power is generated due to a loosely coupled characteristic of the large air-gap. Therefore, we will show you various characteristic of inductive power transfer system as double layer construction of secondary winding, which was divided in half to increase both output current and output voltage, a model of power collector and parallel winding structure, a model of concentration/ decentralization winding and the effects of parameter and operational frequency variation.

Preliminary Research of CZT Based PET System Development in KAERI

  • Jo, Woo Jin;Jeong, Manhee;Kim, Han Soo;Kim, Sang Yeol;Ha, Jang Ho
    • Journal of Radiation Protection and Research
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    • v.41 no.2
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    • pp.81-86
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    • 2016
  • Background: For positron emission tomography (PET) application, cadmium zinc telluride (CZT) has been investigated by several institutes to replace detectors from a conventional system using photomultipliers or Silicon-photomultipliers (SiPMs). The spatial and energy resolution in using CZT can be superior to current scintillator-based state-of-the-art PET detectors. CZT has been under development for several years at the Korea Atomic Energy Research Institute (KAERI) to provide a high performance gamma ray detection, which needs a single crystallinity, a good uniformity, a high stopping power, and a wide band gap. Materials and Methods: Before applying our own grown CZT detectors in the prototype PET system, we investigated preliminary research with a developed discrete type data acquisition (DAQ) system for coincident events at 128 anode pixels and two common cathodes of two CZT detectors from Redlen. Each detector has a $19.4{\times}19.4{\times}6mm^3$ volume size with a 2.2 mm anode pixel pitch. Discrete amplifiers consist of a preamplifier with a gain of $8mV{\cdot}fC^{-1}$ and noise of 55 equivalent noise charge (ENC), a $CR-RC^4$ shaping amplifier with a $5{\mu}s$ peak time, and an analog-to-digital converter (ADC) driver. The DAQ system has 65 mega-sample per second flash ADC, a self and external trigger, and a USB 3.0 interface. Results and Discussion: Characteristics such as the current-to-voltage curve, energy resolution, and electron mobility life-time products for CZT detectors are investigated. In addition, preliminary results of gamma ray imaging using 511 keV of a $^{22}Na$ gamma ray source were obtained. Conclusion: In this study, the DAQ system with a CZT radiation sensor was successfully developed and a PET image was acquired by two sets of the developed DAQ system.

The Desing of GaAs MESFET Resistive Mixer with High Linearity (선형성이 우수한 GaAs MESFET 저항성 혼합기 설계)

  • 이상호;김준수;황충선;박익모;나극환;신철재
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.2
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    • pp.169-179
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    • 1999
  • In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

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Low-Power Sigma-Delta ADC for Sensor System (센서 시스템을 위한 저전력 시그마-델타 ADC)

  • Shin, Seung-Woo;Kwon, Ki-Baek;Park, Sang-Soon;Choi, Joogho
    • Journal of IKEEE
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    • v.26 no.2
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    • pp.299-305
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    • 2022
  • Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

A Calibration-Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High-Matching 3-D Symmetric Capacitors (높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기)

  • Moon, Kyoung-Jun;Lee, Kyung-Hoon;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.55-64
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    • 2006
  • This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

Design and Fabrication of HgI2 Sensor for Phosphor Screen based flat panel X-ray Detector (형광체 스크린 기반 평판형 X선 검출기 적용을 위한 요오드화수은 필름 광도전체 센서 설계 및 제작)

  • Park, Ji Koon;Jung, Bong Jae;Choi, Il Hong;Noh, Si Cheol
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.12
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    • pp.189-194
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    • 2014
  • In this study, from a new x-ray detector that combines a columnar CsI:Na scintillation layer with a photosensitive mercuric iodide layer was investigated. In this structure, X-rays are converted into visible light on a thick CsI:Na layer, which is then converted to electric charges in a thin $HgI_2$ bottom layer. The thin coplanar mercuric iodide films as a photosensitive converter requiring only a few tens of volts of bias, associated with a thick columnar coating of phosphor layer, were simulated and designed. The results of this research suggest that the new coplanar x-ray detector with a hybrid-type structure can resolve the following problems: high voltage from the a-Se, and low conversion efficiency from the indirect conversion method. The results of this research suggest that the new CsI:Na/$HgI_2$ x-ray detector with a double-layer type structure can resolve the following problems: high voltage from the direct conversion method, and low conversion efficiency from the indirect conversion method.

The bidirectional DC module type PCS design for the System Inter Connection PV-ESS of Secure to Expandability (계통 연계 PV-ESS 확장성 확보를 위한 병렬 DC-모듈형 PCS 설계)

  • Hwang, Lark-Hoon;Na, Seung-Kwon;Choi, Byung-Sang
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.14 no.1
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    • pp.56-69
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    • 2021
  • In this paper, the PV system with a link to the commercial system needs some advantages like small capacity, high power factor, high reliability, low harmonic output, maximum power operation of solar cell, and low cost, etc. as well as the properties of inverter. To transfer the PV energy of photovoltaic power generation system to the system and load, it requires PCS in both directions. The purpose of this paper is to confirm the stable power supply through the load leveling by presenting the PCS considering ESS of photovoltaic power generation. In order to achieve these purpose, 5 step process of operation mode algorithm were used according to the solar insolation amount and load capacity and the controller for charging/ discharging control was designed. For bidirectional and effective energy transfer, the bidirectional converter and battery at DC-link stage were connected and the DC-link voltage and inverter output voltage through the interactive inverter were controlled. In order to prove the validity of the suggested system, the simulation using PSIM was performed and were reviewed for its validity and stability. The 3[kW] PCS was manufactured and its test was conducted in order to check this situation. In addition, the system characteristics suggested through the test results was verified and the PCS system presented in this study was excellent and stronger than that of before system.

Probabilistic Reliability Based HVDC Expansion Planning of Power System Including Wind Turbine Generators (풍력발전기를 포함하는 전력계통에서의 신뢰도 기반 HVDC 확충계획)

  • Oh, Ungjin;Lee, Yeonchan;Choi, Jaeseok;Yoon, Yongbeum;Kim, Chan-Ki;Lim, Jintaek
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.1
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    • pp.8-15
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    • 2018
  • New methodology for probabilistic reliability based grid expansion planning of HVDC in power system including Wind Turbine Generators(WTG) is developed in this paper. This problem is focused on scenario based optimal selection technique to decide best connection bus of new transmission lines of HVDC in view point of adequacy reliability in power system including WTG. This requires two kinds of modeling and simulation for reliability evaluation. One is how is reliability evaluation model and simulation of WTG. Another is to develop a failure model of HVDC. First, reliability evaluation of power system including WTG needs multi-state simulation methodology because of intermittent characteristics of wind speed and nonlinear generation curve of WTG. Reliability methodology of power system including WTG has already been developed with considering multi-state simulation over the years in the world. The multi-state model already developed by authors is used for WTG reliability simulation in this study. Second, the power system including HVDC includes AC/DC converter and DC/AC inverter substation. The substation is composed of a lot of thyristor devices, in which devices have possibility of failure occurrence in potential. Failure model of AC/DC converter and DC/AC inverter substation in order to simulate HVDC reliability is newly proposed in this paper. Furthermore, this problem should be formulated in hierarchical level II(HLII) reliability evaluation because of best bus choice problem for connecting new HVDC and transmission lines consideration. HLII reliability simulation technique is not simple but difficult and complex. CmRel program, which is adequacy reliability evaluation program developed by authors, is extended and developed for this study. Using proposed method, new HVDC connected bus point is able to be decided at best reliability level successfully. Methodology proposed in this paper is applied to small sized model power system.

A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications (DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기)

  • Cho, Young-Jae;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.37-47
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    • 2006
  • This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.