• Journal of Satellite, Information and Communications
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• v.11 no.3
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• pp.114-118
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• 2016

In this paper, we present the advanced open collector circuit, interface circuit between aerospace electronics. Satellite is composed of a number of electronics, which were provided from various manufacturers. Each company manufactured its own electronics for satellite using its heritage and requirements for their electronics. Therefore each electronics may use different internal supplies. It make a problem between electronics because the supply is different from other electronics, such as the increasing of power dissipation because of the static current and the mismatch of interface voltage, the offset. Proposed circuit can reduce the static current and rising time, and also decrease the useless power dissipation caused by the static current for open collector circuit

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.594-599
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• 2014

The heat dissipation conditions of high-power 5 watt LEDs-based searchlight modules were optimized with varying LED bar'shape, materials, and ambient temperature. The LED junction temperature was estimated by using Computational Fluid Dynamics simulation. The optimal heat dissipation conditions were found as follows; LED bar' shape: L=80 mm, W=4 mm, t=10 mm, copper material, LED junction temperature of $116.6^{\circ}C$, ambient temperature of $50^{\circ}C$, total mass of 184 g, and shadowing area of $320mm^2$. The difference between the junction temperatures of our fabricated and simulated LEDs-based searchlight modules is about $3^{\circ}C$, which confirms the validity of our thermal simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.589-595
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• 2012

When surges and electromagnetic pulses from lightning or power conversion devices are considered, it is desirable to evaluate grounding system performance as grounding impedance. In the case of large-sized grounding electrodes or long counterpoises, the grounding impedance is increased with increasing the frequency of injected current. The grounding impedance is increased by the inductance of grounding electrodes. This paper presents the measured results of frequency-dependent grounding impedance and impedance phase as a function of the length of counterpoises. In order to analyze the frequency-dependent grounding impedance of the counterpoises, the frequency-dependent current dissipation rates were measured and simulated by the distributed parameter circuit model reflecting the frequency-dependent relative resistivity and permittivity of soil. As a result, the ground current dissipation rate is proportional to the soil resistivity near the counterpoises in a low frequency. On the other hand, the ground current dissipation near the injection point is increased as the frequency of injected current increases. Since the high frequency ground current cannot reach the far end of long counterpoise, the grounding impedance of long counterpoise approaches that of the short one in the high frequency. The results obtained from this work could be applied in design of grounding systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.270-275
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• 2017

Current progress in the development of semiconductor technology in applications involving high electron mobility transistors (HEMT) and power devices is hindered by the lack of adequate ways todissipate heat generated during device operation. Concurrently, electronic devices that use gallium nitride (GaN) substrates do not perform well, because of the poor heat dissipation of the substrate. Suggested alternatives for overcoming these limitations include integration of high thermal conductivity material like diamond near the active device areas. This study will address a critical development in the art of GaN on diamond (GOD) structure by designing for ideal heat dissipation, in order to create apathway with the least thermal resistance and to improve the overall ease of integrating diamond heat spreaders into future electronic devices. This research has been carried out by means of heat transfer simulation, which has been successfully demonstrated by a finite-element method.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.89-93
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• 2018

Ceramic substrates applied to power modules of electric vehicles are required to have properties of high thermal conductivity, high electrical insulation, low thermal expansion coefficient and resistance to abrupt temperature change due to high power applied by driving power. Aluminum nitride and silicon nitride, which are applied to heat dissipation, are considered as materials meeting their needs. Therefore, in this paper, the properties of aluminum nitride and silicon nitride as radiator plate materials were compared through a commercial analysis program. As a result, when the process of applying heat of the same condition to aluminum nitride was implemented by simulation, the silicon nitride exhibited superior impact resistance and stress resistance due to less stress and warping. In terms of thermal conductivity, aluminum nitride has superior properties as a heat dissipation material, but silicon nitride is more dominant in terms of reliability.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.341-346
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• 2017

In this paper, we present a 60 GHz on-off keying (OOK) modulator in a 90 nm CMOS. The modulator employs a current-reuse technique and a switching modulation for low DC power dissipation, high on/off isolation, and high data rate. The measured gain of the modulator, on/off isolation, and output 1-dB compression point is 9.1 dB, 24.3 dB, and 5.1 dBm, respectively, at 60 GHz. The modulator consumes power consumption of 18 mW, and is capable of handling data rates of 8 Gb/s at bit error rate of less than $10^{-6}$ for $231^{-1}$ PRBS over a distance of 10-cm with an OOK receiver module.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.856-859
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• 2002

This paper proposes a high-performance VLSl architecture using distributed arithmetic for higher-order FIR filters with complex coefficients. For the purpose of realizing high sampling rate with small latency in high-order filters, we apply distributed arithmetic[1］. Moreover, in order to decrease drastically the power dissipation, the structure applying not ROM's but optimum function circuits which we have previously proposed, is utilized［2]［3］. However, this structure increases in the number of adders as compared to the conventional structure applying ROM's. In order to realize a more effective method for further higher-order filter, we propose newly an implementation applying two methods which have large effects on the unit using the adders. First , we propose an implementation applying SFAs(Serial Full Adders) and SFSs(Serial Full Subtractors). Second, we propose a structure applying proposed 4-2 adders. Finally, it is shown that the proposed architecture is an effective way to realize low power dissipation and small latency while the sampling rate is kept constant for further higher-order filters with complex coefficients.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.