• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.23-23
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• 2009

Recently, the nanowire configuration of GST showed nanosecond-level phase switch at very low power dissipation, suggesting that the nanowires could be ideal for data storage devices. In spite of many advantages of IST materials, their feasibility in both thin films and nanowires for electronic memories has not been extensively investigated. The synthesis of the chalcogenide nanowires was mainly preformed via a vapor transport process such as vapor-liquid-solid (VLS) growth at a high temperature. However, in this study, IST nanowires as well as thin films were prepared at a low temperature (${\sim}250^{\circ}C$) by metal organic chemical vapor deposition(MOCVD) method, which is possible for large area deposition. The IST films and/or nanowires were selectively grown by a control of working pressure at a constant growth temperature by MOCVD. In-Sb-Te NWs will be good candidate materials for high density PRAM applications. And MOCVD system is powerful for applying ultra scale integration cell.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.470-474
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• 2001

IGBT inverters have switching rise times of 0.2-2 $\mu$ sec, and have been believed to cause insulation stresses and premature motor failures. Inverter driven induction motors with high speed switching and advanced PWM techniques are widely used for variable speed applications. Recently, the insulation failures of stator winding have attracted many concerns due to high dv/dt of IGBT PWM inverter output. In this paper, the detailed insulation test results of 19 low-voltage induction motors are presented. Different types of insulation techniques are applied to 19 motors. The insulation characteristics are analyzed with partial discharge, discharge inception voltage, and dissipation factor tests. Also, breakdown tests by high voltage pulses are performed, and the corresponding breakdown voltages are obtained.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.155-158
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• 2001

A 640Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM, 0.25um CMOS and optical WDM interconnection is fabricated for future N-ISDN services. A 40 layer, 160mm$\times$114mm ceramic MCM realizes the basic ATM switch module with 80Gbps throughput. The basic unit ATM switch module with 80Gb/s throughput. The basic unit ATM switch MCM consists of in 8 chip advanced 0.25um CMOS VLSI and 32 chip I/O Bipolar VLSIs. The MCM employs an 40 layer, very thin layer ceramic MCM and a uniquely structured closed loop type liquid colling system is adopted to cope with the MCM's high-power dissipation of 230w. The MCM is Mounted on a 32cm$\times$50cm mother board. A three stage ATM switch is realized by optical WDM interconnection between the high-performance MCM.

• Transactions on Electrical and Electronic Materials
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• 제4권1호
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• pp.15-20
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• 2003

NiCr alloys are prepared onto poly-Si/ $SiO_2$/Si substrates to replace Pt bottom electrode with a new one for integration of high dielectric constant materials. Alloys deposited at Ni and Cr power of 40 and 40 W showed optimum properties in the composition of N $i_{1.6}$C $r_{1.0}$. The grain size of films increases with increasing deposition temperature. The films deposited at 50$0^{\circ}C$ showed a severe agglomeration due to homogeneous nucleation. The NiCr alloys from the rms roughness and resistivity data showed a thermal stability independent of increasing annealing temperature. The 80 nm thick BST films deposited onto N $i_{1.6}$C $r_{1.0}$/poly-Si showed a dielectric constant of 280 and a dissipation factor of about 5 % at 100 kHz. The leakage current density of as-deposited BST films was about 5$\times$10$^{-7}$ A/$\textrm{cm}^2$ at an applied voltage of 1 V. The NiCr alloys are possible to replace Pt bottom electrode with new one to integrate f3r high dielectric constant materials.terials.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.376-382
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• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

• 한국레이저가공학회지
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• 제18권1호
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• pp.1-6
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• 2015

High welding speed and narrow weld seam are favorable for welding of magnesium alloy. Magnesium alloy is recommended for the smart frame because it has several advantages such as low density, high thermal conductivity, EMI shielding capability and good cast ability. This study is for the assembly welding of the magnesium smart frame with high productivity, good performance and low cost. The window for battery on AZ91D frame produced by die-casting was prepared by CNC machining. Corresponding AZ31 blank of 0.2mm thickness was prepared by die-blanking cut. All system set was fixed at the stationary bed but the laser beam was manipulated by scanner up-to 1,000mm/s speed. The weld joint between AZ31 sheet and AZ91D frame was welded by fiber laser on 850~1,000W output power. The joint showed penetration enough but some humping bead. The distortion by the weld heat was almost free because of the quick dissipation of the heat by small beam size and fast welding. Consequently, the thinner magnesium foil was assembled successfully to the magnesium frame of mobile phone.

• 전기전자학회논문지
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• 제13권1호
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• pp.77-86
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• 2009

본 논문에서 이식형 심장 박동 조율기를 위한 심전도 검출기와 아날로그-디지털 변환기(ADC)를 설계한다. 제안한 웨이블렛 심전도 검출기는 웨이블렛 필터 뱅크 구조의 웨이블렛 변조기, 웨이블렛 합성된 심전도 신호의 가설 검정을 통한 QRS 신호 검출기와 0-교차점을 이용한 잡음 검출기로 구성된다. 저전력 소모의 동작을 유지하며 보다 높은 검출 정확도를 갖는 심전도 검출기의 구현을 위해, 다중스케일 곱의 알고리즘과 적응형의 임계값을 갖는 알고리즘을 사용하였다. 또한 심전도 검출기의 입력단에 위치하는 저전력 Successive Approximation Register ADC의 구현을 위해, 신호 변환의 주기 중, 매우 짧은 시간 동안에만 동작하는 비교기와 수동 소자로 구성되는 Sample&Hold를 사용하였다. 제안한 회로는 표준 CMOS $0.35{\mu}m$ 공정을 사용하여 집적 및 제작되었고, 99.32%의 높은 검출 정확도와 3V의 전원 전압에서 $19.02{\mu}W$의 매우 낮은 전력 소모를 갖는 것을 실험을 통해 확인하였다.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제3권5호
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• pp.151-154
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• 2014

모바일 기기에서 어플리케이션의 에너지 소비는 운영체제, 실행시간 환경, 컴파일러, 어플리케이션 등이 복잡한 상호 작용을 통해 이루어진다. 최근까지 에너지-지향적인 고수준 및 저수준의 컴파일러 기술을 적용하여 모바일 기기에서 어플리케이션의 에너지 소비를 줄이기 위한 노력이 진행되고 있다. 본 논문에서는 안드로이드 달빅에서 실행되는 dex 파일로부터 달빅 바이트코드를 추출한 후 에너지 소비 최적화를 위한 리스트 인스트럭션 스케줄링을 적용하여 어플리케이션의 에너지 소비를 줄이고자 한다. 이러한 연구는 급속도로 확산되고 있는 안드로이드 기반 어플리케이션이 전력 공급이 제한적인 모바일 환경에서 최적화된 전력 에너지 소비할 수 있는 환경을 구축하는 데 활용할 수 있다.

• IEIE Transactions on Smart Processing and Computing
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• 제6권1호
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• pp.27-38
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• 2017

Packet classification is one of the essential functionalities of Internet routers in providing quality of service. Since the arrival rate of input packets can be tens-of-millions per second, wire-speed packet classification has become one of the most challenging tasks. While traditional packet classification only reports a single matching result, new network applications require multiple matching results. Ternary content-addressable memory (TCAM) has been adopted to solve the multi-match classification problem due to its ability to perform fast parallel matching. However, TCAM has a fundamental issue: high power dissipation. Since TCAM is designed for a single match, the applicability of TCAM to multi-match classification is limited. In this paper, we propose a cost- and energy-efficient multi-match classification architecture that combines TCAM with a tuple space search algorithm. The proposed solution uses two small TCAM modules and requires a single-cycle TCAM lookup, two SRAM accesses, and several Bloom filter query cycles for multi-match classifications.