• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.712-719
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• 2012

This paper presents Single-bit Third order Delta-Sigma Modulator, which can be applied to the Low speed High resolution ADC in Audio signal Process System. Whereas the Operational Amplifier in modulator consumed static power dissipation in operating, this modulator used Switching on/off techniques, which makes the Power dissipation of the modulator reduced. Also proposed modulator minimizes frequency characteristic variation by optimizing switch position. And this modulator chooses Single-bit type to guarantee stability. The designed ADC went through 0.35um CMOS n-well 1-poly 4-metal process to be a final product, and the final product has shown 17.1mW of power dissipation with 3.3V of Supply Voltage, 6.4MHz of conversion rate. And 84.3dB SNDR and 13.5bit ENOB with 20KHz of input frequency.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.10
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• pp.213-220
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• 2020

The power consumption and performance of hardware-based mobile and IoT embedded systems that require high specifications are one of the important issues of these systems. In particular, the problem of excessive power consumption is because it causes a problem of increasing heat generation and shortening the life of the device. In addition, in the same environment, software also needs to perform stable operation in limited power and memory, thereby increasing power consumption of the device. In order to solve these issues, we propose a Low level power improvement via identifying performance dissipation. The proposed method identifies complex modules (especially Cyclomatic complexity, Coupling & Cohesion) through code visualization, and helps to simplify low power code patterning and performance code. Therefore, through this method, it is possible to optimize the quality of the code by reducing power consumption and improving performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.5
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1521-1524
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• 1987

The performance of SCF can be improved with the Op-AMP which has the properties of high speed, large slew rate, and lower power dissipation. The OP-AMP used for SCF will be presented. For illustration, using this OP-AMP 5-th order LPF is designed.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2097-2100
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• 1999

Nondestructive and destructive tests were performed the stator windings of three high voltage motors prior to the rewind. Nondestructive tests included ac current increase rate($\Delta$I), dissipation factor(${\Delta}tan{\delta}$), and maximum partial discharge(Qm) The destructive tests included breakdown at three phases with ac voltage. Flashover occurred between the connected winding of endwinding and the stator flame. In two cases creeping discharge occurred between the individual phase windings and the wedges In the stator ends. The results of destructive tests could rarely be determined the breakdown voltage.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.317-328
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• 2016

Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.

• Nuclear Engineering and Technology
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• v.56 no.6
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• pp.2352-2366
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• 2024

Reinforced concrete (RC) shear walls with precast steel-concrete composite modular (PSCCM) are strongly recommended in the structural design of nuclear power plants due to the need for a large number of process pipeline crossings and industrial construction. However, the effect of the PSCCM on the mechanical behavior of the whole RC shear wall is still unknown and has received little attention. In this study, three 1:3 scaled specimens, one traditional shear wall specimen (TW) and two shear wall specimens with the PSCCM (PW1, PW2), were designed and investigated under cyclic loadings. The failure mode, hysteretic curve, energy dissipation, stiffness and strength degradations were then comparatively investigated to reveal the effect of the PSCCM. Furthermore, numerical models of the RC shear wall with different PSCCM distributions were analyzed. The results show that the shear wall with the PSCCM has comparable mechanical properties with the traditional shear wall, which can be further improved by adding reinforced concrete constraints on both sides of the shear wall. The accumulated energy dissipation of the PW2 is higher than that of the TW and PW1 by 98.7 % and 60.0 %. The failure of the shear wall with the PSCCM is mainly concentrated in the reinforced concrete wall below the PSCCM, while the PSCCM maintains an elastic working state as a whole. Shear walls with the PSCCM arranged in the high stress zone will have a higher load-bearing capacity and lateral stiffness, but will suffer a higher risk of failure. The PSCCM in the low stress zone is always in an elastic working state.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.