• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• 소성∙가공
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• 제7권5호
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• pp.450-458
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• 1998

The high temperature deformation behavior of Al 5083 alloy has been studied in the temperature range of 350 to 520 ${\circ}C$ and strain rate range of 0.2 to 3.0/sec by torsion test. The strain rate sensitivity(m) of the material was evaluated and used for estabilishing power dissipation maps following the dynamic material model. These maps show the variation of efficiency of power dissipation(${\eta}$=2m/(2m+1)) with temperature and strain rate. Hot restoration of dynamic recrystallization (DRX) was analyzed from the flow curve, deformed microstructure, and processing maps during hot deformation. Also, the effect of deformation strain on the efficiency of power dissipation of the alloy was analysed using the processing maps. Moreover relationship between the hot-ductility and efficiency of power dissipation of the alloy depending on thmperature and strain rate was studied using the Zener-Hollomon parameter(Z=${\varepsilon}$exp(Q/RT) It is found that the maximum efficiency of power dissipation for DRX in Al 5083 alloy is about 74.6 pct at the strain of 0.2. The strain rate and temperature at which the efficiency peak occurred in the DRX domain is found to be ∼0.1/sec and ∼450${\circ}C$ respectively.

• 전기전자학회논문지
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• 제8권2호
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• pp.181-185
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• 2004

본 논문에서는 산술 연산을 수행하는 연산자의 수가 많은 펑션유닛의 입력 데이터의 스위칭을 최소화하여 소비 전력을 줄인다. 따라서 회로전체의 전력 소모를 줄이기 위해 연산자가 소모하는 전력을 우선적으로 최소화하는 것은 전력 감소의 큰 효과를 가진다. 본 논문은 VLSI회로에서 전력소비에 가장 영향을 많이 미치는 펑션유닛의 연산과정에서 소비하는 전력을 최소화하는 알고리즘을 제안한다. 펑션유닛에서 모든 연산은 전력소비 정보를 가진 전력 라이브러리를 이용하여 피연산자를 스케줄링한다. 전력 라이브러리는 펑션유닛의 모든 입력에 대해 각각의 컨트롤 스텝마다 입력 데이터의 정보를 갱신하고, 그 정보는 스케줄링 과정에서 사용되어진다. 따라서 모든 연산에서 최적화된 데이터를 펑션유닛의 입력으로 하여 전력소비를 최소화 할 수 있다. 본 논문은 상위 레벨 합성 과정에서 펑션유닛에 대한 최소의 전력소비를 위하여 제안하는 알고리즘을 적용하여 실험한 결과 최대 9.4%의 전력 감소효과가 있었다.

• ETRI Journal
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• 제44권3호
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1471-1481
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• 2014

This paper presents the new power dissipation model of individual switching device in a high-level modular multilevel converter (MMC), which can be mostly used in voltage sourced converter (VSC) based high-voltage direct current (HVDC) system and flexible AC transmission system (FACTS). Also, the voltage balancing method based on sorting algorithm is newly proposed to advance the MMC functionalities by effectively adjusting switching variations of the sub-module (SM). The proposed power dissipation model does not fully calculate the average power dissipation for numerous switching devices in an arm module. Instead, it estimates the power dissipation of every switching element based on the inherent operational principle of SM in MMC. In other words, the power dissipation is computed in every single switching event by using the polynomial curve fitting model with minimum computational efforts and high accuracy, which are required to manage the large number of SMs. After estimating the value of power dissipation, the thermal condition of every switching element is considered in the case of external disturbance. Then, the arm modeling for high-level MMC and its control scheme is implemented with the electromagnetic transient simulation program. Finally, the case study for applying to the MMC based HVDC system is carried out to select the appropriate insulated-gate bipolar transistor (IGBT) module in a steady-state, as well as to estimate the proper thermal condition of every switching element in a transient state.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.349-350
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• 2007

Polyethylene is widely used as the insulator for power cable. To investigate the conduction mechanism for power cable insulation under ac high field, it is very important to acquire the dissipation current under actual running field. Recently, we have developed the unique system, which make possible to observe the nonlinear dissipation current waveform. In this system, to observe the nonlinear properties with high accuracy, capacitive current component is canceled by using inverse capacitive current signal instead of using the bridge circuit for canceling it. As the results of these estimations, it was found that the dissipation current will depend on not only the instantaneous value of electric field but also the time differential of applied electric field due to taking a balance between applied field and internal field. Furthermore, two large peaks of dissipation current for each half cycle were observed under certain condition. In this paper, to clarify the reason why it shows two peaks for each half cycle, the film thickness dependences of dissipation current waveforms were observed by using the three different thickness LDPE films.

• 한국인터넷방송통신학회논문지
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• 제18권4호
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• pp.169-175
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• 2018

프로세서의 전력 소비량은 최근에 이르러 고성능 마이크로프로세서 및 멀티코어프로세서 뿐만이 아니라 임베디드 시스템 및 모바일 장치에 매우 중요하게 대두되고 있다. 이러한 전력 소비량은, 하드웨어 및 소프트웨어 설계자로 하여금 성능과 전력에 대한 올바른 타협점을 찾도록 하는 바탕이 된다. 대부분의 전력 분석 도구들은 반도체 칩 레이아웃이나 평면계획이 완료된 후에야 최소의 정확도를 갖게 되며 또한 느리다. 본 논문에서는 전력 분석기와 연동이 가능한 빠른 속도를 갖는 임베디드 마이크로프로세서 명령어 자취형 (trace-driven) 모의실험기를 개발하였다. 또한, MiBench 임베디드 벤치마크를 입력으로 모의실험을 수행하여 기존의 도구보다 훨씬 빠른 속도로 명령어 당 평균 전력 소비량을 측정하였다.

• Journal of Electrical Engineering and Technology
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• 제3권1호
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• 한국인터넷방송통신학회논문지
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• 제16권5호
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• pp.191-196
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• 2016

최근에 이르러, 임베디드 시스템 및 모바일 장치 뿐만이 아니라 고성능 마이크로프로세서 및 멀티코어프로세서의 전력 소비량이 매우 중요하게 대두되고 있다. 특히, 스마트폰과 태블릿 PC의 광범위한 사용으로 인하여 프로세서의 저전력 소비가 무엇보다 요구된다. 본 논문에서는 고성능 마이크로프로세서에 대하여 빠른 속도를 갖는 명령어 자취형 (trace-driven) 모의실험기 기반의 전력 측정기를 개발하였다. 본 전력 측정기는 마이크로프로세서를 구성하는 복합 조합회로, 배열구조, CAM 구조를 기반으로 하였으며, SPEC 2000 벤치마크를 입력으로 모의실험을 수행하여 각 벤치마크의 평균 전력 소비량을 측정하였다.

• ETRI Journal
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• 제33권1호
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.