• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.467-472
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• 2006

This study has been done to design a precise system and develop position control algorithm to control a Composite Smoke Bomb Azimuth driving apparatus of a BLDC servo motor. Having to Blind the sight of opposite tank. the Smoke Bomb Rotational driving system needs instant response that is able to detect opponent appearance and blast the bomb at a short time. So a design that shows fast current response capability or $300[Hz]\sim500[Hz]$ is proposed. in the MIN-MAX PWM technology is used to increase the operational speed. in order to control the blasting position, a precision position control algorithm that utilizes the integral value of speed trajectory is suggested. Also these characteristics are monitored and assessed by the PC based monitoring program which shows the graphs of current, voltage, position, and speed parameters. The main controller is based on a TMS320VC33 high performance floating-point DSP(Digital Signal Process) and the PWM generator utilizes EPM7128 CPLD.

• Transactions of the Korean Society of Automotive Engineers
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• v.22 no.2
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• pp.166-174
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• 2014

Fuel injection pressure has steadily increased in diesel engines for the purpose of improving fuel efficiency and cleaning exhaust gas, but it has now reached a point, where the cost for higher pressure does not warrant additional gains. Common rail systems on modern diesel engines have fuel pumps that are mechanically driven by crankshaft. The pumps actually house two pumping module inside: a low pressure pump component and a high pressure pump component. Part of the fuel compressed by the low pressure component returns to the tank in the process of maintaining the pressure in the common rail. Since the returning fuel represents pumping loss, fuel economy improves if the returned fuel can be eliminated by using a properly controled electrical fuel pump. As the first step in developing an electrical fuel pump the fuel supply system on a 6 liter diesel engine was modeled with AMESim to analyze the workload and the fuel feed rate of the injection pump, and the results served as basis for selecting a suitable servo motor and a reducer to drive the pump. A motor controller was built using a DSP and a program which controls the common rail pressure using a proportional control method based on the target fuel pressure information from the engine ECU. A test rig to evaluate performance of the fuel pump is implemented and used to show that the newly developed electrically driven fuel pump can satisfy the fuel flow demand of the engine under various operating conditions when the rotational speed of the pump is adequately controlled.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.119-128
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• 2011

This paper introduces design space exploration of many-core processors that meet high performance and low power required by the beamforming algorithm of image signals of mobile ultrasound. For the design space exploration of the many-core processor, we mapped different number of ultrasound image data to each processing element of many-core, and then determined an optimal many-core processor architecture in terms of execution time, energy efficiency and area efficiency. Experimental results indicate that PE=4096 and 1024 provide the highest energy efficiency and area efficiency, respectively. In addition, PE=4096 achieves 46x and 10x better than TI DSP C6416, which is widely used for ultrasound image devices, in terms of energy efficiency and area efficiency, respectively.

• Journal of IKEEE
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• v.24 no.1
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• pp.19-24
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• 2020

This paper presents a 3-level, 2-level SVPWM technique with 100 kHz switching using Verilog HDL, one of the languages of FPGA. In the case of IGBT devices mainly used in inverters, they have a switching frequency around 20kHz. Recent research and development of next-generation power semiconductor devices such as GAN has enabled switching of more than 100kHz, which can miniaturize power converters, and apply various new algorithms due to the injection of harmonics. In the existing system using the IGBT, the control using the DSP is common, but the controller configuration for 100 kHz switching requires the use of FPGA. Therefore, this paper explains the theory and implementation of SVPWM applied to two-level and three-level inverters using FPGAs and verifies the performance through the output waveform. In addition, this paper implements 3-level SVPWM by using only one carrier instead of using two carriers in the conventional method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.647-655
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• 2008

This paper presents real-time algorithm for an ultrasonic Local Positioning System(LPS). An ultrasonic LPS consists of 4 transmitters and n receivers. Each transmitter transmits an sequential ultrasonic signal to avoid interference of ultrasonic signal. This method is a noneffective application for a fast object. Because receiver detects four sequential transmissive ultrasonic signal and calculates a position. This paper proposes the method which 4 transmitters transmit simultaneous ultrasonic signal and each transmitter distinguished by frequencies and codes. And Auto-Correlation Function(ACF) method separates codes from an ultrasonic echo signal which is interference of each transmitter's code. If the receiver uses only ACF method, it is difficult to implement real time application for increased computation. This paper implements LPS using dual frequencies and ACF method. Using dual frequencies reduces codes length. The reduced codes length save computation in ACF. To prove this algorithm by experiment, high performance DSP(digital signal processor) used. The result shows the performance of the designed system is good enough positioning.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.4 s.97
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• pp.163-177
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• 1999

Polishing work for a curved surface die demands simple and repetitive operations and requires much time while it demands also high precision. Therefore it is operated by a skilled worker in handiwork. However the workers avoid gradually a polishing work because of the poor environmental conditions such as dust and noise. In order to reduce the polishing time and to alleviate the problem of shortage of skilled workers, an automatic polishing robot system which is composed of a polishing robot with two degrees of freedom motion and pneumatic system is developed, and it is attached to machining center with three degrees of freedom. The system keeps the polishing tool vertically on the surface of die and maintains constant pneumatic pressure. The polishing robot with DSP(digital signal processor) controller is controlled by sliding mode control. A synchronization between machining center and polishing robot is accomplished by using M code of machining center. A performance experiment for polishing work is executed by the developed automatic polishing robot system. The result shows that the developed automatic polishing robot has a good performance and well polished workpiece surface is obtained.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.81-86
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• 2023

Recently, demand for embedded systems requiring low power and high specifications has been increasing, and RISC-V processors are being widely applied. RISC-V, a RISC-based open instruction set architecture (ISA), has been developed and researched by UC Berkeley and other researchers since 2010. RV32I ISA is sufficient to support integer operations such as addition and subtraction instructions, but M-extension should be defined for multiplication and division instructions. This paper proposes an RV32I, RV32IM processor, and indicates benchmark performance scores compared to an existing processor. Additionally, A non-stalling method was proposed to support a 2-stage pipelined DSP multiplier to the 5-stage pipelined RV32IM processor. Proposed RV32I and RV32IM processors satisfied a maximum operating frequency of 50 MHz on Artix-7 FPGA. The performance of the proposed processors was verified using benchmark programs from Dhrystone and Coremark. As a result, the Coremark benchmark results of the proposed processor showed that it outperformed the existing RV32IM processor by 23.91%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1172-1176
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• 2008

In this paper, we describe the implementation and performance of a dual-mode Software Define Radio (SDR) smart antenna base station system. SDR technology enables a communication system to be reconfigured through software downloads to the flexible hardware platform that is implemented using programmable devices such as Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), and microprocessors. The presented base station channel card comprises the physical layer (pHY) including the baseband modem as well as the beamforming module. This channel card is designed to support TDD High-Speed Downlink Packet Access (HSDPA) as well as Wireless Broadband Portable Internet (WiBro) utilizing the SDR technology. We first describe the operations and functions required in WiBro and TDD HSDPA. Then, we explain the channel card design procedure and hardware implementation. Finally, we evaluate WiBro and TDD HSDPA performance by simulation and actual channel-card-based processing. Our smart antenna base-station dual-mode channel card shows flexibility and tremendous performance gains in terms of communication capacity and cell coverage.