• Title/Summary/Keyword: High Level Modulation

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Analysis and Control of NPC-3L Inverter Fed Dual Three-Phase PMSM Drives Considering their Asymmetric Factors

  • Chen, Jian;Wang, Zheng;Wang, Yibo;Cheng, Ming
    • Journal of Power Electronics
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    • v.17 no.6
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    • pp.1500-1511
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    • 2017
  • The purpose of this paper is to study a high-performance control scheme for neutral-point-clamping three-level (NPC-3L) inverter fed dual three-phase permanent magnet synchronous motor (PMSM) drives by considering some asymmetric factors such as the non-identical parameters in phase windings. To implement this, the system model is analyzed for dual three-phase PMSM drives with asymmetric factors based on the vector space decomposition (VSD) principle. Based on the equivalent circuits, PI controllers with feedforward compensation are used in the d-q subspace for regulating torque, where the cut-off frequency of the PI controllers are set at the twice the fundamental frequency for compensating both the additional DC component and the second order component caused by asymmetry. Meanwhile, proportional resonant (PR) controllers are proposed in the x-y subspace for suppressing the possible unbalanced currents in the phase windings. A dual three-phase space vector modulation (DT-SVM) is designed for the drive, and the balancing factor is designed based on the numerical fitting surface for balancing the DC link capacitor voltages. Experimental results are given to demonstrate the validity of the theoretical analysis and the proposed control scheme.

Dual Vector Control Strategy for a Three-Stage Hybrid Cascaded Multilevel Inverter

  • Kadir, Mohamad N. Abdul;Mekhilef, Saad;Ping, Hew Wooi
    • Journal of Power Electronics
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    • v.10 no.2
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    • pp.155-164
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    • 2010
  • This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

Three Phase Three-Level Switched Voltage Source PWM Inverter with Zero Neutral Point Potential (영 전위 중성점을 가진 새로운 3상 Three-Level 스위치 전압원 인버터)

  • Oh Won-Sik;Han Sang-Kyoo;Choi Seong-Wook;Moon Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2004.07b
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    • pp.630-634
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    • 2004
  • A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. The major advantage is that the peak value of the phase output voltage is twice as high as that of the conventional neutral-point-clamped (NPC) PWM inverter. Furthermore, three-level waveforms of the proposed inverter can be achieved without switch voltage unbalance problem. Since the average neutral point potential of the proposed inverter is zero, the common ground between input stage and output stage is possible. The proposed inverter is verified by experimental results based on a laboratory prototype.

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PWM Control Techniques for Single-Phase Multilevel Inverter Based Controlled DC Cells

  • Sayed, Mahmoud A.;Ahmed, Mahrous;Elsheikh, Maha G.;Orabi, Mohamed
    • Journal of Power Electronics
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    • v.16 no.2
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    • pp.498-511
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    • 2016
  • This paper presents a single-phase five-level inverter controlled by two novel pulse width modulation (PWM) switching techniques. The proposed PWM techniques are designed based on minimum switching power loss and minimum total harmonic distortion (THD). In a single-phase five-level inverter employing six switches, the first proposed PWM technique requires four switches to operate at switching frequency and two other switches to operate at line frequency. The second proposed PWM technique requires only two switches to operate at switching frequency and the rest of the switches to operate at line frequency. Compared with conventional PWM techniques for single-phase five-level inverters, the proposed PWM techniques offer high efficiency and low harmonic components in the output voltage. The validity of the proposed PWM switching techniques in controlling single-phase five-level inverters to regulate load voltage is verified experimentally using a 100 V, 500 W laboratory prototype controlled by dspace 1103.

A SVPWM for the Small Fluctuation of Neutral Point Current in Three-level Inverter (중성점 전류 리플을 고려한 3-레벨 인버터의 공간 벡터 펄스폭 변조 기법)

  • 김래영;이요한;현동석
    • Proceedings of the KIPE Conference
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    • 1998.11a
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    • pp.33-37
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    • 1998
  • For the high power variable speed applications, the DCTLI(diode clamped three-level inverter) have been widely used. This paper describes the analysis of the neutral point current of the DCTLI and the improved space vector-based PWM strategy considering the switching frequency of power devices, that minimizes the fluctuation of the neutral point current in spite of high modulation index region and low power factor. It contributes to decrease the capacitance of dc-link capacitor bank and to increase the neutral point voltage controllable region. Especially, even if second (or even) order harmonic is induced in load current (at this situation, is was investigated that the general control method can not suppress the neutral point voltage variation), this PWM can provide effective control method to suppress the neutral point voltage variation. Various simulation results by means of Matlab/Simulation are presented to verify the proposed PWM.

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MODELING, ANALYSIS AND CONTROL OF STATIC VAR COMPENSATOR USING THREE-LEVEL INVERTER (3-레벨 인버터를 사용한 무효전력 보상기의 모델링, 해석 및 제어기 설계)

  • Cho, Guk-C.;Choi, Nam-S.;Cho, Gyu-H.
    • Proceedings of the KIEE Conference
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    • 1993.07b
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    • pp.764-766
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    • 1993
  • A new static var compensator(SVC) system using three-level inverter is proposed for high voltage and high power applications. A general and simple model for the overall system is obtained using circuit DQ-transform and DC and AC analyses are achieved to characterize the open-loop system. Using the proposed model, a new control method which controls both the phase angle and modulation index of switching pattern simultaneously is suggested to provide fast response of SVC system without using independent voltage source. Finally, predicted results are verified by computer simulation.

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Development of a Signal Conditioning Circuit for Capacitive Displacement Sensors and Performance Evaluation (정전용량형 변위 센서 신호 처리 회로 개발 및 성능 평가)

  • Kim, Jong-Ahn;Kim, Jae-Wan;Eom, Tae-Bong;Kang, Chu-Shik
    • Journal of the Korean Society for Precision Engineering
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    • v.24 no.9
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    • pp.60-67
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    • 2007
  • A signal conditioning circuit for capacitive displacement sensors was developed using a high frequency modulation/demodulation method, and its performance was evaluated. Since capacitive displacement sensors can achieve high resolution and linearity, they have been widely used as precision sensors within the range of several hundred micrometers. However, they inherently have a limitation in low frequency range and some nonlinearity characteristics and so a specially designed signal conditioning circuit is needed to handle these properties. The developed signal processing circuit consists of three parts: linearization, modulation/demodulation, and nonlinearity compensation. Each part was constructed discretely using several IC chips and passive elements. An evaluation system for precision displacement sensors was developed using a laser interferometer, a precision stage, and a PID position controller. The signal processing circuit was tested using the evaluation system in the respect of resolution, repeatability, linearity, and so on. From the experimental results, we know that a highly linear voltage output can be obtained successfully, which is proportional to displacement and the nonlinearity of output is less than 0.02% of full range. However, in the future, further investigation is required to reduce noise level and phase delay due to a low-pass filter. The evaluation system also can be applied effectively to calibration and evaluation of precision sensors and stages.

PWAM Based THD Reduction of Inverter for Air-Conditioning Blower (PWAM 방식을 이용한 공조시스템용 인버터의 THD 저감 방법)

  • Lim, Seung-Beom;Lee, Yun-Ha;Zun, Chan-Yong
    • Proceedings of the KIPE Conference
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    • 2011.07a
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    • pp.97-98
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    • 2011
  • The HVAC(Heating Ventilation and Air conditioning) system is controlled by two ways, one is ON/OFF control and the other is PWM inverter with V/F. Control of blower with the use of PWM inverter has quite some benefits such as the capability of changing speed, high efficiency and reduced noise level compared with ON/OFF control. But if blower is operated at low speed, high THD generated by decrease of ma, and output voltage lowered in proportion to frequency. To solve these problems, filter should be installed at the output stage of inverter, which can decrease THD but has problems such as increase of volume size and additional braking resistance. This paper proposes the PWAM method which can reduce THD instead of installing the filter at the output stage of inverter. The proposed PWAM method is an inverter modulation method that fixes the modulation index of inverter to reduce THD by varying DC link voltage of inverter unlike conventional PWM method. Finally, the validity of proposed PWAM methods verified by experiments.

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A Design of 16-QAM Modulator by use of Direct Digital Frequency Synthesizer (디지탈 직접 주파수 합성기를 이용한 16-QAM 변조기 설계)

  • 유상범;유흥균
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.5
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    • pp.52-57
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    • 1999
  • It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.

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3GPP GERAN Evolution System Employing High Order Modulation and Turbo Coding: TSC for Channel Estimation (터보코딩 및 고차변조를 적용하는 3GPP GERAN 진화 시스템: 채널 추정을 위한 TSC)

  • Lee, Jong-Hwan;Hwang, Eun-Sun;Choi, Byoung-Jo;Hwang, Seung-Hoon;Choi, Jong-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.6A
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    • pp.599-606
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    • 2008
  • In this paper, the channel estimation performance of proposed TSC (TSC-S) is investigated in terms of the BER and BLER performances when HSR is considered for GERAN evolution system. The performance is evaluated by the link level simulation and is compared with the other TSC proposal (TSC-E). Numerical results show that the performance employing the TSC-S is almost same to that using the TSC-E. In the case of cochannel interferences, the similar tendency is shown, when joint least square is adopted for channel estimation.