• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.489-493
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• 2002

This paper discover another boost vectors in high modulation index In steady states, modulation index of converter operation is normally $0.7\~0.8[p.u]$. Even though zero vectors are not imposed, DC-Link voltage is constant because 3-level boost convert has another boost vectors. and this paper proposes the analysis and the comparison for NPC and H-Bridge converter. It proposed the calculation method for the voltage ripple and charging current of each capacitor and deals with voltage balance problems of each link capacitor they are associated with the switching state, the position of reference voltage vector. Simulation and analysis are used in order to prove validity of the proposed methods.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.59-65
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• 1999

There has been an interest to develop an efficient, compact microwave device using field-emitter-arrays (FEA)-based cathode. Toe valuate the optimum device-efficiency in a compact size, the propagation properties of the premodulated electron beam for the FEA-based cathode is studied in detail by the computer simulation using a PIC code, MAGIC. For the premodulated electron beam whose phase of the energy leads the phase of the current by $\pi$/2, the amplitude of the downstream current modulation can be kept as high as the initial modulation level. Using the beam parameters with the beam voltage of 6kV and the current of 2.0A, 30% of efficiency is predicted when the quality factor of 800 is chosen. the device length is reduced about twice compared with that of the conventional device. The design of practical planar cathode is carried out to meet the minimum diameter of the electron beam as 0.5 mm.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.9-12
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• 2001

In DS/CDMA system the number of output signal levels increases as multi-channel signals are summed, hence the power amplifier with high linearity is required. PW/CDMA is a transmission technique that performs pulse width modulation on the multilevel signal synthesized from multiple channel data. In PW/CDMA system the signal level is maintained to be binary, hence the modulation and demodulation circuits become simple. In this paper we derive the probability of bit error of the PW/CDMA system in AWGN environment. The results are compared with DS/CDMA system and are verified through the computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.809-811
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• 2015

In this paper, for the purpose of providing high data rate services, the multi-hop frame structure is designed for the underwater acoustic (UWA) short-range system which is proposed as a part of ocean surveillance and tracking network (OSTN). Under the measured underwater channel environment, the link-level system performance are also evaluated. Simulation results show not only the packet error rate (PER) comparisons, but the optimal modulation and coding scheme (MCS) levels for the orthogonal frequency division multiplexing (OFDM) based short-range UWA communications network.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.69-72
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• 2000

Multilevel modulation schemes are known to be highly bandwidth efficient. By varying modulation level adaptively according to channel conditions (i.e. adaptive QAM schemes or AQAM), high bandwidth efficiency can be achieved. This paper considers the effect of time delay on the adaptive QAM schemes in dispersive fading channels. In order to undertake investigations effectively, a simulator has been developed. The simulation results show that the BER performance obtained for the wideband channel with a delay spread of 0.75 $\mu$sec is better than 10$^{-4}$ with a SNR value of 40 ㏈ and ABPS is found to be approximately 5.5.

• Journal of Power Electronics
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• v.14 no.3
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• pp.478-487
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• 2014

This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at $V_{in}/2$. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.11
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• pp.4419-4435
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• 2015

The use of an efficient packet scheduling scheme for a forward link in satellite communication networks is very important to support fairness for each return channel satellite terminal (RCST) and the service differentiations for user traffics. To support fairness and QoS for each RCST with service-level agreement (SLA), the Adaptive Coding and Modulation (ACM) system in a satellite hub has to process packets with considering modulation and coding (MODCOD) and packet types. Although a DVB-S2 system with ACM scheme has higher transmission efficiency, it cannot offer fairness or quality of service (QoS) to RCSTs. Because the data are transmitted with high MODCOD in regions with clear skies, while data are transmitted using low MODCOD in regions experiencing rain events. In this paper, we propose a two-step scheduling scheme offering fairness and QoS to RCSTs, while minimizing a decrease in throughput. The proposed scheme is carried out performance evaluations using a computer simulation. As results of this simulation, the proposed scheduler was shown to support bandwidth fairness to an individual RCST, and provide a level of QoS differentiation for user traffics.

• Journal of Electrical Engineering and Technology
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• v.8 no.2
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• pp.304-315
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• 2013

In this paper, analysis of cascaded H-bridge multilevel inverter in DTC-SVM (Direct Torque Control-Space Vector Modulation) based induction motor drive for FCEV (Fuel Cell Electric Vehicle) is presented. Cascaded H-bridge multilevel inverter uses multiple series units of H-bridge power cells to achieve medium-voltage operation and low harmonic distortion. In FCEV, a fuel cell stack is used as the major source of electric power moreover the battery and/or ultra-capacitor is used to assist the fuel cell. These sources are suitable for utilizing in cascaded H-bridge multilevel inverter. The drive control strategy is based on DTC-SVM technique. In this scheme, first, stator voltage vector is calculated and then realized by SVM method. Contribution of multilevel inverter to the DTC-SVM scheme is led to achieve high performance motor drive. Simulations are carried out in Matlab-Simulink. Five-level and nine-level inverters are applied in 3hp FCEV induction motor drive for analysis the multilevel inverter. Each H-bridge is implemented using one fuel cell and battery. Good dynamic control and low ripple in the torque and the flux as well as distortion decrease in voltage and current profiles, demonstrate the great performance of multilevel inverter in DTC-SVM induction motor drive for vehicle application.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1500-1511
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• 2017

The purpose of this paper is to study a high-performance control scheme for neutral-point-clamping three-level (NPC-3L) inverter fed dual three-phase permanent magnet synchronous motor (PMSM) drives by considering some asymmetric factors such as the non-identical parameters in phase windings. To implement this, the system model is analyzed for dual three-phase PMSM drives with asymmetric factors based on the vector space decomposition (VSD) principle. Based on the equivalent circuits, PI controllers with feedforward compensation are used in the d-q subspace for regulating torque, where the cut-off frequency of the PI controllers are set at the twice the fundamental frequency for compensating both the additional DC component and the second order component caused by asymmetry. Meanwhile, proportional resonant (PR) controllers are proposed in the x-y subspace for suppressing the possible unbalanced currents in the phase windings. A dual three-phase space vector modulation (DT-SVM) is designed for the drive, and the balancing factor is designed based on the numerical fitting surface for balancing the DC link capacitor voltages. Experimental results are given to demonstrate the validity of the theoretical analysis and the proposed control scheme.