• Journal of Power Electronics
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• 제15권2호
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• pp.443-454
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• 2015

This study proposes a novel one-cycle control scheme with a plug-in repetitive controller for load compensator. The novelty of this scheme lies in the combination of high dynamics and the simplicity of a one-cycle controller and good steady-state harmonic suppression ability of the repetitive controller. In addition, the proposed scheme can reduce the effect of the harmonics in phase voltage for the existence of the repetitive controller. Finally, experimental results on a three-phase, four-wire, three-level load compensator are reported to validate the effectiveness of the proposed control scheme.

• 한국전자파학회논문지
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• 제16권9호
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• pp.909-916
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• 2005

본 논문에서는 기본 공진 주파수($f_o$)에서 단락 부하를 갖는 기존 $\lambda$/4-마이크로스트립 공진기의 Q값과 2차 직렬 공진 주파수(2$f_o$)가 천이되는 문제를 해결하여 2차 고조파 제거특성을 개선한 새로운 구조의 마이크로스트립 공진기를 제안하였으며 제안된 마이크로스트립 공진기는 마이크로웨이브 및 밀리미터 대역에서 비선형 회로들의 고조파 제거 특성을 개선하는데 적용할 수 있을 것이다.

• Journal of Electrical Engineering and Technology
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• 제3권3호
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• pp.373-378
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• 2008

In this paper, an Active Power Filter (APF) is implemented using a dSPACE DS1104 processor to compensate harmonics and reactive power produced by nonlinear load. The reference source current is computed based on the measurement of harmonics in the supply voltage and load current. A hysteresis based current controller has been implemented in a DSP processor for injecting the compensating current into the power system, so that APF allows suppression of the harmonics and reactive power component of load current, resulting in a supply current that is purely sinusoidal. Simulation and experimental results of the proposed APF to meet the IEEE-519 standards are presented.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.608-614
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• 2015

A multi-channel audio CODEC with inter-channel interference suppression is proposed, in which channel switching noise-referred sampling error is significantly reduced. It also supports a coarse/fine mode operation for fast frequency tracking with good harmonic performance. The proposed multi-channel audio CODEC was designed in a 65 nm CMOS process. Measured results indicated that SNR and SNDR of ADC were 93 dB and 84dB, respectively, with SNDR improved by 43 dB. Those of DAC were 96 dB and 87 dB, respectively, with SNDR improved by 45 dB when all the channels are running independently.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1577-1579
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• 1994

200-MW pulse modulators(total 11units) for the PLS linac employ the SCR phase control circuit. It controls 3-phase AC line voltage for the high-voltage DC power supply (DCPS, maximum of 25kVDC, 4.2A) which charges the pulse forming network(PFN). The PFN delivers 400kV, 500A, ESW $7.5{\mu}s$ pulse power to the 80-MW klystron amplifier tube. The SCR regulates 3-phase AC power and feeds to the high voltage transformer. Two different types of the transformer configurations namely ${\Delta}-{\Delta}$ and ${\Delta}-Y$, are alternatively installed to 11 modulator units for the suppression of harmonic noises. RC filters and reactors are also installed. Currently, approximately 110-kW of average AC power per unit is consumed at the normal operation level of the modulator with 30pps. This paper presents the operational characteristics of the high power pulse modulator, especially the experimental results of the AC line harmonic components generated by the operation of the high power pulse modulator to suppress the switching noises from the SCR and rectifying diode arrays.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권8호
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• pp.405-412
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• 2003

This paper presents a three-phase Line-Interactive uninterruptible power supply (UPS) system with series-parallel active power-line conditioning capabilities, using synchronous reference frame (SRF) based controller, which allows an effective power factor correction, source harmonic voltage compensation, load harmonic current suppression, and output voltage regulation. The three-phase UPS system consists of two active power compensator topologies. One is a series active compensator, which works as a voltage source in phase with the source voltage to have the sinusoidal source current and high power factor under the deviation and distortion of the source voltage. The other is a parallel active compensator which works as a conventional sinusoidal voltage source in phase with the source voltage, providing to the load a regulated and sinusoidal voltage with low THD (total harmonic distortion). The control algorithm using SRF method and the active power flow through the Line-interactive UPS systems are described and studied. The simulation and experimental results are depicted in this paper to show the effect of the proposed algorithm.

• Journal of Power Electronics
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• 제17권6호
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• pp.1683-1693
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• 2017

This paper analyses the harmonic pollution to power grids caused by thyristor-controlled devices. It also formulates a mathematic derivation for the voltage spikes in thyristor-controlled branches to explain the harmonic and EMI derived from the reverse-recovery characteristics of the thyristor. With an equivalent nonlinear time-varying voltage source, a detailed simulation model is established, and the periodic dynamic switching characteristic of the thyristor can be explicitly implied. The simulation results are consistent with the probed results from on-site measurements. An improved trigger system with gate-shorted circuit structure is proposed to reduce the voltage spikes that cause EMI. The experimental results indicate that a prototype with the improved trigger system can effectively suppress the voltage spikes.

• 한국ITS학회 논문지
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• 제14권6호
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• pp.110-116
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• 2015

본 논문은 T 형태의 미엔더 선로를 적용한 브랜치 라인 커플러를 이용하여 고조파가 억압된 소형 저손실의 반사기 형태인 위상 변위기에 대해 제안을 한다. 위상 변위기의 소형 커플러는 $22.2{\times}14.9mm^2$의 크기를 갖고 있으며, 기존의 브랜치 커플러는 $32.6{\times}27.8mm^2$의 크기를 나타낸다. 본 논문에서 제안된 위상 변위기는 2.1 GHz의 중심 주파수에서 삽입손실 0.19~0.28 dB, 그리고 $137^{\circ}$의 최대 위상 변위를 보여주고 있다.

• Journal of electromagnetic engineering and science
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• 제16권3호
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• pp.191-193
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• 2016

This paper proposes a voltage-controlled oscillator (VCO) that has broadband turning and low-level of phase noise characteristics. Due to the micro-strip line resonant circuit with a low Q value, which is applied to the broadband tuning range, the depreciated phase noise performance is compensated by restraining the harmonics of the oscillating frequency. The VCO was designed according to the proposed structure as well as the conventional structure, and the superiority of the proposed structure was verified through its simulation, fabrication, and measurement.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 I
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• pp.294-297
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• 2003

This paper describes the design and the simulation of a frequency doubler for millimeter-wave applications using distributed amplifier technology. The designed frequency multiplier has 10% bandwidth at 58GHz output. This paper investigates nonlinear analysis of pHEMT frequency multipliers utilizing AM-AM and AM-PM distortion characteristics of frequency doubler. The conversion loss is 2.1dB and harmonic suppression is larger than 18.6dBc with 5dBm input power