• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.137-142
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• 2006

A large portion of the embedded system development process involves the integration of hardware and software. Unfortunately, communication across the hardware/software boundary is tedious and error-prone to create. This paper presents an automatic hardware/software interface generation system. As the front-end of hardware/software co-design frameworks, a system designer defines XML specifications for hardware functions. Our system generates hardware/software interfaces including Device Driver, Driver API, and Device Controller from these specifications. Embedded software designers can easily use hardware just like system libraries. Our system reduces the mistakes and errors that can be occurred when a software programmer directly connects software to hardware, and supports balancing labors between hardware developers and software programmers. Moreover, this system can be used as the back-end for a hardware/software co-design framework.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• International Journal of Contents
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• v.7 no.1
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.305-308
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• 2002

This paper proposes a control board that includes PNP function with extensibility and effective allocation of allocation. The object of study is to overcome limited extensity of old systems and it is to reuse the system. The system recognizes automatic subsystem from application of main system with board level that is using hardware and software co-design method. The system has both function of main-board and sub-board. So one system can operate simultaneously such as module of alien system. This system has advantages that are fast execution, according as process functional partition to hardware/ software co-design and board size is reduced as well as offer extensity of development system. We obtained good result with control board for existent Z-80 training kit.

• Journal of Digital Contents Society
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• v.5 no.1
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• pp.61-65
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• 2004

This paper presents a method of constructing the embedded systems based on hardware/software co-design approach that was key methodology. The proposed method was important technology enable to implement advanced multimedia systems and digital contents creating that are rapidly growing of the new information technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.641-642
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• 2011

This paper presents method of constructing the embedded systems based on hardware-software codesign which is the important fields of $21^{st}$ information technology. First, we describe the classification and necessity of embedded systems, and we discuss the consideration and classification for constructing the embedded systems. Also, we discuss the embedded systems modeling. The proposed embedded systems based on hardware-software co-design is important gradually, we expect that it involve the many IT fields in the future.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.481-484
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• 2007

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.7
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• pp.1480-1483
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• 2009

In this paper, the hardware(HW) and software(SW) co-design methodology of H.264/AVC decoder using ARM-Excalibur is proposed. The SoC consists of embedded processor, memory, peripheral device and logic circuits. Recently, the co-design method which designs simultaneously HW and SW part is a new paradigm in SoC design. Because the optimization for partitioning the SoC system is very difficult, the verification must be performed earlier in design flow. We designed the H.264 and AVC Decoder using co-design method. It is shown that, for the proposed co-design method, the performance improvements can be obtained.

• Journal of Convergence Society for SMB
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• v.3 no.1
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• pp.31-41
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• 2013

There have been various recent methods proposed in detecting driver drowsiness (DD) to avert fatal accidents. This work proposes a hardware/software (HW/SW) co-design approach in implementation of a DD detection system adapted from an AdaBoost-based object detection algorithm with Haar-like features [1] to monitor driver's eye closure rate. In this work, critical functions of the DD detection algorithm is accelerated through custom hardware components in order to speed up processing, while the software component implements the overall control and logical operations to achieve the complete functionality required of the DD detection algorithm. The HW/SW architecture was implemented on an Altera DE2 board with a video daughter board. Performance of the proposed implementation was evaluated and benchmarked against some recent works.