• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.419-424
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• 2015

The era of IoT in which all objects are intelligent and are connected to the Internet has been started. In order to establish and activate an IoT eco system, open services platform is very important. In this paper, we developed a BLE sensor module as a component of the open service platform based on the IoT and the open source hardware Blutooth4.0. To verify the functionality and performance of the developed BLE sensor module was built to evaluate the performance of the test environment.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.517-519
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• 2005

In this paper, we consider a digital protection IED(Intelligent Electric Device) for a distributed power system. The IED can measure various elements for protection and communicate with another devices through network. The protection IED is composed of specific function modules: signal process module which converts analog signal from PT and CT handle algorithm to digital one; communication module for connection with another IEDs; input/output module for user-interfaces. A general purpose DSP board with TMS320C2812 is used in the IED. In order to verify the proposed IED, experimental researches with the power system simulator DOBLE has been carried out for a phase earth fault. The results show an under-voltage relaying algorithm has been realized sucessfully in the hardware system.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.420-421
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• 2010

In this paper, a multi-module selective battery equalizer for series-connected Li-ion battery pack is proposed. Selective Equalizer (SE) scheme achieves smaller volume and lighter weight than individual cell equalizer (ICE) by minimizing the part count of bulky circuit element. However, SE scheme shows slow balancing speed when the voltage imbalance simultaneously occurs in more than one cell. The proposed multi-module overcomes the problem by employing multiple power converters. Prototype hardware is implemented and experimented with 14Ah battery cells to validate the performance of the proposed equalizer.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.204-210
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• 1988

The residue number system offers the possibility of high-speed operation and error detection/correction because of the separability of arithmetic operations on each digit. A compact residue arithmetic module named the self-checking pulse-train residue arithmetic circuit is effectively employed as the basic module, and an efficient error detection/correction algorithm in which error detection is performed in each basic module and error correction is performed based on the parallelism of residue arithmetic is also employed. In this case, the error correcting circuit is imposed in series to non-redundant system. This design method has an advantage of compact hardware. Following the proposed method, a 2nd-order recursive fault-tolerant digital filter is practically implemented, and its fault-tolerant ability is proved by noise injection testing.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.49-57
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• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.488-493
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• 2006

Accurate river discharge is the most important factor in managing river basins and for successfully maintaining total maximum daily loads in Korea. It is not easy to measure the discharge directly in large rivers owing to physical and environmental constraints, even after investing much time and money. Recently, to overcome these historical drawbacks in river discharge measurement, we have developed the Automatic Discharge Acquisition & Management System (ADAMS) that scans the river cross-section and measures each cell $(1m{\times}1m)$ velocity using HADCP. The hardware system is composed of an HADCP sensor and winch, as well as a PC and software system for the discharge calculation module and hardware control module. It is controlled remotely via the internet and uses the velocity-depth integration method and the velocity-contour method for calculating river discharges. The characteristics of ADAMS are a ubiquitously accessible system, featuring real time automatic discharge measurement, remote control via the internet. The results using ADAMS at the Jindong stage site show less than 5% uncertainty and are 4 times more efficient than the ADCP & Q-boat system. This system can be used to measure any large river, river mouth or tributary river affected by backwater, all of which have a very difficult measuring real time discharge. The next generation of ADAMS will feature an upgrade to increase portability and GPS integration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.334-339
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• 2012

A study on electrical and electronic equipment will occur in the atmosphere, which is essential to cut the power to prevent the waste of power by power measurement technology development and to develop the technology to do this operation is the main core of standby power to detect and block it and return the configured for software and hardware, while the actual construction to ensure stability through field testing and debugging of problems improved accordingly, as well as ease of installation and so it could be done while the test. In addition, in terms of basic hardware switching of standby power when blocking, reducing stress and ensure stable operation and circuit design, power off and back to ensure stable operation even when a protection circuit is applied.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.237-240
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• 2012

This paper describes an implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-core supports three master key lengths of 128/192/256-bit specified in the standard and the four modes of operation including ECB, CBC, CTR and OFB. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. The ARIA crypto-core is verified by FPGA implementation, the estimated throughput is about 1.07 Gbps at 167 MHz.