• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• Journal of Information Processing Systems
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• v.2 no.3 s.4
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• pp.137-142
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• 2006

A large portion of the embedded system development process involves the integration of hardware and software. Unfortunately, communication across the hardware/software boundary is tedious and error-prone to create. This paper presents an automatic hardware/software interface generation system. As the front-end of hardware/software co-design frameworks, a system designer defines XML specifications for hardware functions. Our system generates hardware/software interfaces including Device Driver, Driver API, and Device Controller from these specifications. Embedded software designers can easily use hardware just like system libraries. Our system reduces the mistakes and errors that can be occurred when a software programmer directly connects software to hardware, and supports balancing labors between hardware developers and software programmers. Moreover, this system can be used as the back-end for a hardware/software co-design framework.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.34 no.3
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• pp.49-56
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• 2011

Estimating optimum hardware capacity of an e-learning system is very important process to grasp reasonable size of designing technique architecture and budget during step of ISP(information strategic planning) and development. It hugely influences cost and quality of the whole project. While investment on information system hardware has been continuously increased, there was no certified hardware capacity estimating method in e-learning system development. A guideline for hardware sizing of information systems was established by Telecommunication Technology Association in 2008. However, the guideline is not appropriate for estimating optimum hardware capacity of an e-learning system because it was designed to provide general standards for estimating hardware capacity of various types of projects. The purpose of this paper is to provide a methodology for estimating optimum hardware capacity in e-learning system development. To develop the methodology, this study, first of all, analyzes two e-learning development projects, in which the guideline was applied to estimate optimum hardware capacity. Then, this study finds out several key factors influencing on hardware capacity. Finally, this study suggests a methodology for estimating optimum hardware capacity of an e-learning system, in which weights for the factors are determined through AHP analysis.

• 전자공학회논문지 IE
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• v.46 no.2
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• pp.7-10
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• 2009

This paper presents the implementation of libraries of hardware modules for genetic algorithm using VHDL. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results and analysis for several fitness functions. It can be seen that our design works well for the three examples.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.4
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• pp.839-845
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• 2018

Sensitive data is encrypted and stored as privacy policy is strengthened through frequent leakage of personal information. For this reason, the cryptographically owned encrypted data is a very important analysis from the viewpoint of digital forensics. Until now, the digital evidence collection procedure only considers imaging, so hardware specific information is not collected. If the encryption key is generated by information that is not left in the disk image, the encrypted data can not be decrypted. Recently, an application for performing encryption using hardware specific information has appeared. Therefore, in this paper, hardware specific information which does not remain in file form in auxiliary storage device is studied, and hardware specific information collection method is introduced.

• Journal of Information Technology Services
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• v.5 no.1
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• pp.47-59
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• 2006

According to the policy for "e-Korea construction" of Korean government, Investment of information system during the past decade are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in terms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinate empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.6
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• pp.1294-1310
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• 2010

User authentication using fingerprint information provides convenience as well as strong security. However, serious problems may occur if fingerprint information stored for user authentication is used illegally by a different person since it cannot be changed freely as a password due to a limited number of fingers. Recently, research in fuzzy fingerprint vault system has been carried out actively to safely protect fingerprint information in a fingerprint authentication system. In addition, research to solve the fingerprint alignment problem by applying a geometric hashing technique has also been carried out. In this paper, we propose the hardware architecture for a geometric hashing based fuzzy fingerprint vault system that consists of the software module and hardware module. The hardware module performs the matching for the transformed minutiae in the enrollment hash table and verification hash table. On the other hand, the software module is responsible for hardware feature extraction. We also propose the hardware architecture which parallel processing technique is applied for high speed processing. Based on the experimental results, we confirmed that execution time for the proposed hardware architecture was 0.24 second when number of real minutiae was 36 and number of chaff minutiae was 200, whereas that of the software solution was 1.13 second. For the same condition, execution time of the hardware architecture which parallel processing technique was applied was 0.01 second. Note that the proposed hardware architecture can achieve a speed-up of close to 100 times compared to a software based solution.

• Journal of Internet Computing and Services
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• v.21 no.2
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• pp.109-119
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• 2020

The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.

• Proceedings of the Korea Association of Information Systems Conference
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• 2005.12a
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• pp.307-313
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• 2005

According to the Policy for ' e-Korea construction ' of Korean government, investment of information system during the Past decay are dramatically increasing. More than a half of this investment is cost of hardware infrastructure. So, accurate hardware sizing are essential for higher efficiency of investment. Accurate hardware sizing benefits are generally viewed in toms of the avoidance of excess equipment and lost opportunity costs by not being able to support business needs. Unfortunately, however, little research effort to make the hardware sizing methodology are doing. We propose a sizing method for information system in public sector. This method is determinated empirical study that are gathering and analyzing cases, making method and reviewing expert. Finally we are proposed calculating method for hardware components that is CPU, memory, internal and external disk according to the application system type which is OLTP, Web, WAS. Our study certainly will act as a catalyst for higher investment-efficiency of the future information programs in public sector.

• Journal of the Korea Society of Computer and Information
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• v.22 no.8
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• pp.47-53
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• 2017

In this paper, we present open hardware platforms for Internet of Things (IoTs) emphasizing their strengths and weaknesses. We introduce six representative platforms, Raspberry PI, Arduino, Garileo, Edison, Beagle board and Artik. We define important performance issues for open hardware platforms for IoTs and analyze recent platforms according to the performance issues. We present recent research project using open hardware platforms introduced in this paper. We believe that this paper provide wise view and necessary information for open hardware platforms for Internet of Things (IoT).