• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Journal of Korea Game Society
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• v.8 no.3
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• pp.43-50
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• 2008

UI design is growing in meaning and form itself through the development of hardware and contents. And it makes users accept its interface as a extension of the body and mind because of the substantial rapport of the user and contents with developing of device and graphic. In this study, we analyzed user interface in a view of digital storytelling by observing of its role within user and contents. Not only this, classifying and investigating story elements in the games for forming the theoretical basis of storytelling UI are enforced. For the case study of UI, we choose the game, Diablo, Half-Life, and Homeworld because the game is suitable for the application of node-type storytelling and effectively uses graphic and input unit. This analysis explains the interface has the contents data that divided or shared and it means the interface performs its part of story nodes, which are extracted from the story, and choice. And we analogized that the story elemental can be substituted and used practically for interface because the stories made through the thing that users and developers are in the space of coexistence by the interface. Storytelling UI will be a good way to make a most intriguing piece as a joyful spontaneous complex that use story node. It is worth by reason of making by user and discovering live inner story so that it can approach to the substance of the story.

• Journal of Navigation and Port Research
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• v.29 no.1 s.97
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• pp.91-96
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• 2005

The National Marine Electronics Association(NMEA) is nonprofit-making cooperation composed with manufacturers, distributors, wholesalers and educational institutions. We use the basic port of equipment in order to process the signal from NMEA signal using equipment. When we don't have enough one, we use the multi-port for processing. However, we need to have module development simulation which could multiplex and provide NMEA related signal that we could solve the problems in multi-port application and exclusive equipment generation for a number of signal. For now, we don't have any case or product using NMEA multiplexer so that we import expensive foreign equipment or embody NMEA signal transmission program like software, using multi-port. These have problems since we have to pay lots ci money and build separate processing part for every application programs. Besides, every equipment generating NMEA signal are from different manufactures and have different platform so that it could cause double waste and loss of recourse. For making up for it, I suggest the NMEA multiplexer embodiment, which could independently move by reliable process and high performance single hardware module, improve the memory efficiency of module by designing the optimized Queue, and keep having reliability for realtime communication among the equipment such as main input sensor equipment Gyrocompass, Echo-sound, and GPS.

• Journal of Broadcast Engineering
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• v.25 no.1
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• pp.25-35
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• 2020

Recently, the development of image processing technology, as well as hardware performance, has been continuing the research on 3D point processing technology that provides users with free viewing angle and stereoscopic effect in various fields. Point cloud technology, which is a type of representation of 3D point, has attracted attention in various fields because it can acquired/expressed point precisely. However, since Hundreds of thousands, millions of point are required to represent one 3D point cloud content, there is a disadvantage that a larger amount of storage space is required than a conventional 2D content. For this reason, the MPEG (Moving Picture Experts Group), an international standardization organization, is continuing to research how to efficiently compress, store, and transmit 3D point cloud content to users. In this paper, a V-PCC bitstream generated by a V-PCC (Video-based Point Cloud Compression) encoder proposed by the MPEG-I (Immersive) group is composed of an MPU (Media Processing Unit) defined by the MMT. In addition, by extending the signaling message defined in the MMT standard, a parameter for a segmented transmission method of the 3D point cloud content by area and quality parameters considering the characteristic of the 3D point cloud content, so that the quality parameters can be selectively determined according to the user's request. Finally, in this paper, we verify the result through design/implementation of the verification platform based on the proposed technology.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.867-879
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• 2006

This paper concerns fast and time accurate HW/SW cosimulation for MPSoC(Multi-Processor System-on-chip) architecture where multiple software and/or hardware components exist. It is becoming more and more common to use MPSoC architecture to design complex embedded systems. In cosimulation of such architecture, as the number of the component simulators participating in the cosimulation increases, the time synchronization overhead among simulators increases, thereby resulting in low overall cosimulation performance. Although SystemC cosimulation frameworks show high cosimulation performance, it is in inverse proportion to the number of simulators. In this paper, we extend the novel technique, called virtual synchronization, which boosts cosimulation speed by reducing time synchronization overhead: (1) SystemC simulation is supported seamlessly in the virtual synchronization framework without requiring the modification on SystemC kernel (2) Parallel execution of component simulators with virtual synchronization is supported. We compared the performance and accuracy of the proposed parallel SystemC cosimulation framework with MaxSim, a well-known commercial SystemC cosimulation framework, and the proposed one showed 11 times faster performance for H.263 decoder example, while the accuracy was maintained below 5%.

• KIPS Transactions on Computer and Communication Systems
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• v.7 no.1
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• pp.9-18
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• 2018

Enhancing performance of big data analytics in distributed environment has been issued because most of the big data related applications such as machine learning techniques and streaming services generally utilize distributed computing frameworks. Thus, optimizing performance of those applications at Spark has been actively researched. Since optimizing performance of the applications at distributed environment is challenging because it not only needs optimizing the applications themselves but also requires tuning of the distributed system configuration parameters. Although prior researches made a huge effort to improve execution performance, most of them only focused on one of three performance optimization aspect: application design, system tuning, hardware utilization. Thus, they couldn't handle an orchestration of those aspects. In this paper, we deeply analyze and model the application processing procedure of the Spark. Through the analyzed results, we propose performance optimization schemes for each step of the procedure: inner stage and outer stage. We also propose appropriate partitioning mechanism by analyzing relationship between partitioning parallelism and performance of the applications. We applied those three performance optimization schemes to WordCount, Pagerank, and Kmeans which are basic big data analytics and found nearly 50% performance improvement when all of those schemes are applied.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.34-41
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• 2002

In the conventional rake receiver structure for the IS-95 CDMA system, each finger has its own time-deskew buffer or FIFO that aligns the multipath signals to the same timing reference in order to combine symbols. This architecture is not a burden to the rake receiver design mainly because of the small number and size of the buffers. However, the number and size of the buffers are significantly increased in the cdma2000 system which adopts multiple carriers and the small spreading gain for a higher rate in data services. In order to decrease the number of buffers, we propose a new model of the time-deskew buffers, which combines the symbols as well as realigns them at the same time. Our architecture reduces the hardware complexity of the buffers by about more than 60% and 70% compared with the conventional one when we consider each rake receiver has three and four independent fingers, respectively. Moreover, the proposed algorithm is very useful not only to the cdma2000 rake receiver but also to the receiver with many fingers in order to increase the BER performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.1-8
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• 2010

A digital phase wrapping modulation (DPM) open-loop polar transmitter can be efficiently applied to a wideband orthogonal frequency division multiplexing (OFDM) communication system by converting in-phase and quadrature signals to envelope and phase signals and then employing the signal mapping process. This mapping process is very similar to quantization in a general communication system, and when taking into account the error that appears during mapping process, one can replace the coordinates rotation digital computer (CORDIC) algorithm in the coordinate conversion part with the Taylor series approximation method. In this paper, we investigate the application of the Taylor series approximation to the cartesian to polar coordinate conversion part of a DPM polar transmitter for wideband OFDM systems. The conventional approach relies on the CORDIC algorithm. To achieve efficient application, we perform computer simulation to measure mean square error (MSE) of the both approaches and find the minimum approximation order for the Taylor series approximation compatible to allowable error of the CORDIC algorithm in terms of hardware design. Furthermore, comparing the processing speeds of the both approaches in the implementation with FPGA reveals that the Taylor series approximation with lower order improves the processing speed in the coordinate conversion part.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.