• Journal of KIISE:Computing Practices and Letters
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• v.8 no.3
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• pp.261-267
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• 2002

In SOC(System On a Chip) designs, reducing time and cast for design verification is the most critical to improve the design productivity. this is mainly because the designs require co-verifying HW together with SW, which results in the increase of verification complexity drastically. In this paper, to cope with the verification crisis in SOC designs, we propose a new verification methodology, so called integrated co-verification, which lightly combine both co-simulation and co-emulation in unified and seamless way. We have applied our integrated co-verification to ARM/AMBA platform-based co-verification environment with a commercial co-verification tool, Seamless CVE, and a physical prototyping board. The experiments has shown clear advantage of the proposed technique over conventional ones.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.485-488
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• 2009

The class of BCH codes is a large class of error correction codes. HDL implementation of BCH code generator to change code rate. and used System Generator, and implemented hardware to FPGA. Loaded bit stream to a FPGA board in order to verify this design to Hardware co-simulation from these results. Also, compared as investigated the maximum action frequency through timing analysis and resource of logic in order to evaluate performance of BCH code generator.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.41-46
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• 2010

In this paper, the DoA(Direction of Arrival) estimator using unitary MUSIC algorithm is studied. The complex-valued correlation matrix of MUSIC algorithm is transformed to the real-valued one using unitary transform for easy implementation. The eigenvalue and eigenvector are obtained by the combined Jacobi-CORDIC algorithm. CORDIC algorithm can be implemented by only ADD and SHIFT operations and MUSIC spectrum computed by 256 point DFT algorithm. Results of unitary MUSIC algorithm designed by System Generator for FPGA implementation is entirely consistent with Matlab results. Its performance is evaluated through hardware co-simulation and resource estimation.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.2
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• pp.8-17
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• 2008

This paper presents the Matlab/Simulink-based software-in-the-loop simulation(SILS) environment which is the co-simulator for temporal and functional simulations of control systems. The temporal behavior of a control system is strongly dependent on the implemented software and hardware such as the real-time operating system, the target CPU, and the communication protocol. The proposed SILS abstracts the system with tasks, task executions, real-time schedulers, and real-time networks close to the implementation. Methods to realize these components in graphical block representations are investigated with Matlab/Simulink, which is most commonly used tool for designing and simulating control algorithms in control engineering. In order to achieve a seamless development from SILS to rapid control prototyping (RCP), the SILS block-set is designed to support automatic code generation without tool changes and block modifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.47-55
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• 2012

This paper describes the developed HILS and test equipment in order to test the performances of MMW(Millimeter-Wave) seeker which can detect and track a high speed of short-range ballistic missile and aircraft. This system is used to 141 horn antenna array, array switching, and gain and phase control algorithm to simulate various kind of targets and trajectory of high speed and maneuver moving target. In addition, it simulates not only velocity and range for these targets but also clutter and jamming environments. System configuration and implementation and the measurement results of major subsystems such as target motion simulator, simulation signal generator, high speed data aquisition unit, and central control unit are presented. These systems could verify the detection and tracking performance of MMW seeker through dynamic real-time test based on simulation flight scenario.

• Journal of the Semiconductor & Display Technology
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• v.13 no.1
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• pp.73-81
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• 2014

In this paper, high-speed Hybrid MAC (Medium Access Control layer) implementation suitable for smart grid applications is researched. MB-OFDM (Multi-Band Orthogonal Frequency Division Multiplexing) is considered for high-speed communication method in smart grid application. In this paper, the MAC adopts the distributed network managing method. Also, the MB-OFDM merit of high-speed transfer rate of up to 480Mbps must be supported. Hence, this paper presents an efficient hardware-software integration (co-design) method in order to realize a high- speed transmission, and a realizing method of distribution network. Finally, MAC performance and reliability based on MB-OFDM PHY (PHYsical layer) are confirmed through simulation and emulation.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.177-178
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• 2007

WiBro system provides reliable broadband communication services for mobile and portable subcribers. It allows interference-free reception under the conditions of multipath propagation and transmission errors. Thus, powerful channel-error correction ability Is required. CC/CTC Decoder which Is mandatory for WiBro system needs lots of computations for real-time operation. So, it is desired to design a CC/CTC Decoder having highly optimized hardware scheme for low latency operation under high data rates. This paper proposes an efficient CC/CTC Decoder structure for high data rate WiBro system. Particularly, the proposed CTC Decoder architecture reduces decoding delay by applying pipelining and multiple decoding blocks. Simulation results show that reduction of about 80% of processing time is enabled with the proposed CC/CTC Decoder despite of increase in are.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1972-1977
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• 2005

In this work, an inverse dynamic control method is developed to enhance tracking performance of industrial robots, which effectively deal with the nonlinear dynamic interferential forces. In general, the DFF (Dynamic Feed-Forward) controller and the CTM (Computed-Torque Method) controller are used for dynamic control for industrial robots. We study on the practical issues for implementing these inverse dynamic controllers via simulations and experiments. We develop the dynamic models in two different ways. One is a model designed through Newton-Euler method for real time computation and the other is a model designed through SimMechanics for evaluating the developed controller via simulations. We evaluate the nominal performance and robustness of the controller via simulations and experiments using serial 4-DOF HyRoHILS (Hyundai Robot Hardware-In-the-Loop Simulation) system. The results show that the inverse dynamic controller is effective and practically useful for a real control structure.

• Journal of Aerospace System Engineering
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• v.13 no.6
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• pp.36-42
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• 2019

This research illustrates how the simulation environment for operating the simultaneous man/unmanned aerial vehicle teaming is constructed. X-Plane program, HILS for the ducted fan aircraft (unmanned) and CTLS (manned aircraft) with communication devices are interfaced to simulate the basic co-operational flight. The X-plane and HILS can allow operators to experience the maned and unmanned aircraft operation in the airspace on the ground in turn they can perform various simulated missions in advance before the actual flight. For the test purpose, the data link between man/unmanned aircraft and ground control station is examined using C Band and UHF radio channels by the manned aircraft.