• Journal of Information Processing Systems
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• v.9 no.3
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• pp.499-510
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• 2013

Hardware-Software co-simulation of a multiple image encryption technique shall be described in this paper. Our proposed multiple image encryption technique is based on the Latin Square Image Cipher (LSIC). First, a carrier image that is based on the Latin Square is generated by using 256-bits of length key. The XOR operation is applied between an input image and the Latin Square Image to generate an encrypted image. Then, the XOR operation is applied between the encrypted image and the second input image to encrypt the second image. This process is continues until the nth input image is encrypted. We achieved hardware co-simulation of the proposed multiple image encryption technique by using the Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. We validated our proposed technique by using the hardware software co-simulation method.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1047_1048
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• 2009

This paper describes comparative analysis results about the dynamic interaction of interconnected wind power system using the actual-size hardware simulator and the simulation model with PSCAD/EMTDC. The hardware simulator, which is composed of 2.0MVA induction motor with drive system and 1.5MW doubly-fed induction generator, was built and tested in Go-Chang Test Site of KEPCO for analyzing the dynamic interaction with the interconnected distribution system. The operation of hardware simulator was verified through comparative analysis between experimental results and simulation results obtained by simulation model with PSCAD/EMTDC. The developed hardware simulator and simulation model could be effectively used for analyzing the dynamic interaction, which has various phenomena depending on the wind variation and the network state of interconnected power system.

• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.110-115
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• 2014

The reconfigurability of FPGA devices allows designers to evaluate, test and validate a new control algorithm; a new component or prototypes without damaged the real system with the so-called hardware co-simulation. The present paper uses the Xilinx System Generator (XSG) environment to establish and validate a new nonlinear estimator for the rotor time constant inverse that will be exploited to improve the indirect rotor field control of induction motor.

• Journal of Internet of Things and Convergence
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• v.1 no.1
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• pp.33-38
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• 2015

Hardware are developed in various architecture. It is necessary to verifying value of variables in modules generated in each clock cycles for timing simulation. In this paper, a test vector generator in software type generates test vectors for timing simulation of 224-bit ECDSA hardware modules in developing stage. It provides test vectors with GUI format and text file format.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.906-911
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• 2008

This paper designed Simulik Model to cancel the carrier frequency offset in OFDM using CORDIC Algorithm and evaluated its performance. And Simulink Model compared with Xilinx System Generator Model for FPGA implementation. As a result of simulation, we confirmed that both model is error free by CORDIC when offset frequency is lower than $10^5MHz$. Also, we verified the performance through Hardware Co-simulation with Xilinx Spartan3 xc3s1000 fg676-4 Target Device, and timing analysis and resource estimation.

• Journal of Ocean Engineering and Technology
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• v.30 no.5
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• pp.367-373
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• 2016

This paper describes the development of a navigation HILS (hardware in the loop simulation) system for an integrated navigation performance analysis of a large diameter unmanned underwater vehicle (LDUUV). The HILS system was used for the performance analysis of the LDUUV. When a conventional HILS system is used, it is not possible to calculate the velocity and position using an inertial navigation system (INS). To cope with this problem, an external acceleration was generated. To evaluate the proposed method, we compare the results of a Monte Carlo simulation and navigation HILS experiment.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.354-358
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• 2001

Cosim (Hardware and Software Co-Simulator) is a JavaBeans-based simulation tool fur validating systems architecture and estimating performance of web applications. Cosim has four components: Modeler, Translator, Engine and Scenario. Users start from Modeler to describe systems architecture in UML(Unified Modeling Language) deployment diagram, and then specify hardware & software performance parameters such as execution delay, network topology, and frame size. All information specified on Modeler are sent to Translator, and then automatically converted to Java programs. Scenario is responsible to run the Java program and produce results in text reports and graphs. Developers can reduce development time and cost by validating systems architecture of web applications before the actual deployment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.898-905
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• 2018

In this work, infrared targets for a developed hardware-in-the-loop simulation(HILS) system are proposed for a performance test of a dual-sensor imaging seeker equipped with an infrared and a visible sensor that can lock and track for ground and air targets. This integrated system is composed of 100 modules of heat and light sources to simulate various kinds of target and the trajectory of moving targets based on scenarios. It is possible to simulate not only the position, velocity, and direction for these targets but also background clutter and jamming environments. The design and measurement results of an infrared target, such as the HILS system configuration, developed for testing and evaluation of a dual-sensor imaging seeker are described. In the future, it is planned to test the lock-on and tracking performance of an imaging seeker equipped with single or dual sensors dynamically in real time based on a simulation flight scenario in the developed HILS system.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.