• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.999-1002
• /
• 2005

This paper describes an improved Rate-Distortion Optimization Algorithm for JPEG2000. We proposed a new optimal constant setting method and rate allocation method to reduce execution time of the rate control. And we proposed hardware structure of the improved R-D opti. algorithm. Consequently, improved Rate-Distortion Optimization algorithm is faster than conventional rate control scheme in JPEG2000 standard and have nearly same performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3256-3264
• /
• 1996

This paper presents an efficient VLSI architecture for transposing matris in high speed. In the case of transposing N*N matrix, N$^{2}$ numbers of transposition cells are configured as regular and spuare shaped structure, and pipeline structure for operating each transposition cell in paralle. Transposition cell consists of register and input data selector. The characteristic of this architecture is that the data to be transposed are divided into several bundles of bits, then processed serially. Using the serial transposition of divided input data, hardware complexity of transpositioncell can be reduced, and routing between adjacent transposition cells can be simple. the proposed architecture is designed and implemented with 0.5 .mu.m VLSI library. As a result, it shows stable operation in 200 MHz and less hardware complexity than conventional architectures.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.1787-1790
• /
• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.31B no.6
• /
• pp.10-16
• /
• 1994

In case of off-line character recognition with statistical method, the character recognition speed for Korean or Chinese characters is slow since the amount of calculation is huge. To improve this problem, we seperate the recognition steps into several functional stages and implement them with hardwares for each stage so that all the stages can be processed with pipline structure. In accordance with temporal parallel processing, a high speed character recognition system can be implemented. In this paper, we implement a classification hardware, which is one of the several functional stages, to improve the speed by parallel structure with multiple DSPs(Digital Signal Processors). Also, it is designed to be able to expand DSP boards in parallel to make processing faster as much as we wish. We implement the hardware as an add-on board in IBM-PC, and the result of experiment is that it can process about 47-times and 71-times faster with 2 DSPs and 3 DSPs respectively than the IBM-PC(486D$\times$2-66MHz). The effectiveness is proved by developing a high speed OCR(Optical Character Recognizer).

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.629-630
• /
• 2006

This paper presented a hardware implementation of ARIA, which is Korean standard block ciphering algorithm. In this work, we proposed a improved architecture based on pipeline structure and confirmed that the design operates in a clock frequency of 101.7MHz and in throughput of 957Mbps in Xilinx FPGA XCV-1600E.

• Journal of information and communication convergence engineering
• /
• v.9 no.1
• /
• pp.27-31
• /
• 2011

This paper describes the optimization of spectrum sensing in terms of the throughput of a cognitive radio (CR) system. Dealing with the optimization problem of spectrum sensing, this paper evaluates the throughput of a CR system by considering such situations as the penalty time of a channel search and incumbent user (IU) detection delay caused by a missed detection of an incumbent signal. Also, this paper suggests a serial channel search scheme as the search method for a vacant channel, and derives its mean channel search time by considering the penalty time due to the false alarm of a vacant channel search. The numerical results suggest the optimum sensing time of the channel search process using the derived mean channel search time of a serial channel search in the case of a sensing hardware structure with single radio frequency (RF) path. It also demonstrates that the average throughput is improved by two separate RF paths in spite of the hardware complexity of an RF receiver.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.5 no.4
• /
• pp.18-25
• /
• 1996

In this study, we have developed the stereolithography system that supports the development of a products. This paper presents the development of the stereolithography system. The system is composed of hardware, software and control part. The software converts a STL file to NC data and displays the monitoring figure in control part. The hardware part deals with structure of machine. The most important theme in this paper is LG-SLCAM software. This software can generate NC data and scanning condition data from a STL file semiautimatically. On the basis of three diensional shapes, it makes data for support structure from STL file. The effectiveness of using out stereolithography system is confirmed by processes of good development.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.4
• /
• pp.321-328
• /
• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.53 no.1
• /
• pp.1-9
• /
• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.7 s.349
• /
• pp.50-57
• /
• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.