• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.575-577
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• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.578-580
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• 2017

IoT technology poses a lot of security threats. Various algorithms are thus employed in ensuring security of transactions between IoT devices. Advanced Encryption Standard (AES) has gained huge popularity among many other symmetric key algorithms due to its robustness till date. This paper presents a hardware based implementation of the AES algorithm. We present a four-stage pipelined architecture of the encryption and key generation. This method allowed a total plain text size of 512 bits to be encrypted in 46 cycles. The proposed hardware design achieved a maximum frequency of 1.18GHz yielding a throughput of 13Gbps and 800MHz yielding a throughput of 8.9Gbps on the 65nm and 180nm processes respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.17 no.4
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• pp.53-62
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• 2021

Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.

• Journal of the Korea Society of Computer and Information
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• v.12 no.2 s.46
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• pp.63-70
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• 2007

The Data Encryption Standard (DES) is a block cipher that encrypts a 64 bit block of plaintext into a 64 bit block of ciphertext. The DES has been a worldwide standard for 20 years since it was adopted in 1976. strong. But, due to the rapid development of hardware techniques and cryptanalysis, the DES with 64-bit key is considered to be not secure at the present time. Therefore it became necessary to increase the security of DES. The NG-DES(New Generation DES)[1] is an encryption system which upgrades the encryption security of DES by the key extension and the usage of non-linear f function. It extends not only the size of plaintext and ciphertext to 128 bit but also the Fiestel structure used in each round. This structure has a weak point that the change of each bit of plaintext does not affect all bits of ciphertext simultaneously. In this paper, we propose a modified Fiestel structure of DES and thus increased confusion and diffusion by effectively cross-connecting between outputs in a round and inputs in next round.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.122-125
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• 2003

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1037-1040
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• 1999

In this paper, we designed the extended ATA(AT Attachment interface with extension) interface that combines with goods price and ability and intellectual behavior of SCSI, for make progress the ability and structure of ordinary interface for connect with device of using PC. ATA is establish a standard of IDE(Intelligent Drive Electronics) public in small form factor. SCSI bus is device behaving intellectual and have stable hardware structure, calssified instructions structure. But it is device that difficult to buy, because of price of more than two times. The other side, ATA device is worse than SCSI bus in part of ability, but it came to SCSI in part of speed after improve and it's price is less expensive. another improvement of ATA is a standard of ARAP(AT Attachment Packet Interface) and use method of packet transmission and behaves as if SCSI use a method. Finally, improvement of ATAPI behave from interface of only HDD to ability of ordinary interface. This paper propose the structure of extended interface that satisfied the price and ability.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.7 s.94
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• pp.1813-1822
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• 1993

An algorithm of fuzzy variable structrue control is proposed to design a closed loop fuel-injection system for the emission control of automotive gasoline engines. Fuzzy control is combined with sliding control at the switching boundary layer to improve the chattering of the stoichiometric air to fuel ratio. Multi-staged fuzzy rules are introduced to improve the adaptiveness of control system for the various operating conditions of engines, and a simplified technique of fuzzy inference is also adopted to improve the computational efficiency based on nonfuzzy micro-processors. The proposed method provides an effective way of engine controller design due to its hybrid structure satisfying the requirements of robustness and stability. The great potential of the fuzzy variable structure control is shown through a hardware-testing with an Intel 80C186 processor for controller and a typical engine-only model on an AD-100 computer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.1
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• pp.51-58
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• 2012

This paper deals with the development of educational system for Architectural Structure Engineering based on PBL(Problem-Based Learning). To develop this educational system, firstly, the eduction process for Architectural Structure Engineering is suggested by reviewing PBL and creativity. The suggested educational system is composed with hardware of structural model and courseware can be utilized in the education process. In this courseware, softwares for testing structures and teaching recommendations are involved. Finally, merits of this system in the real application are suggested and the complementariness are discussed for a future search.