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http://dx.doi.org/10.17662/ksdim.2021.17.4.053

Sparse Matrix Compression Technique and Hardware Design for Lightweight Deep Learning Accelerators  

Kim, Sunhee (상명대학교, 시스템반도체공학과)
Shin, Dongyeob (한국전자기술연구원, 스마트네트워크연구센터)
Lim, Yong-Seok (한국전자기술연구원, 스마트네트워크연구센터)
Publication Information
Journal of Korea Society of Digital Industry and Information Management / v.17, no.4, 2021 , pp. 53-62 More about this Journal
Abstract
Deep learning models such as convolutional neural networks and recurrent neual networks process a huge amounts of data, so they require a lot of storage and consume a lot of time and power due to memory access. Recently, research is being conducted to reduce memory usage and access by compressing data using the feature that many of deep learning data are highly sparse and localized. In this paper, we propose a compression-decompression method of storing only the non-zero data and the location information of the non-zero data excluding zero data. In order to make the location information of non-zero data, the matrix data is divided into sections uniformly. And whether there is non-zero data in the corresponding section is indicated. In this case, section division is not executed only once, but repeatedly executed, and location information is stored in each step. Therefore, it can be properly compressed according to the ratio and distribution of zero data. In addition, we propose a hardware structure that enables compression and decompression without complex operations. It was designed and verified with Verilog, and it was confirmed that it can be used in hardware deep learning accelerators.
Keywords
Accelerator; Bitmap; Compression; Decompression; Sparse Matrix;
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