• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.117-119
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• 2004

An optimal flight motion simulator path generation method is proposed for hardware in the loop simulation of high maneuverable missile. The proposed method consists of open loop and closed loop path calculation algorithm based on the energy optimal control strategies. The optimal angle command is able to protect the simulator from high acceleration shock at initial control phase.

• 한국정보통신학회논문지
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• 제14권7호
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• pp.1723-1728
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• 2010

본 논문에서는 뮤직 콘텐츠의 무분별한 사용의 피해를 줄이고 대형 매장과 임의의 공간과 공간사이 다른 콘텐츠를 서비스 할 수 있는 Multi-Channel Internet Radio Platform 에 대해 설계 방안을 제공하고 구현 연구를 진행한다. 본 플랫폼은 Multi-Channel Connection을 위한 Application 설계방법과 그에 따른 Multi Stream을 위한 Hardware Path를 구현하는 방법 제안 및 구현 결과를 제공한다.

• International Journal of Advanced Culture Technology
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• 제7권4호
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• pp.313-320
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• 2019

Nowadays, as the availability of tiny, low-cost microcomputer increases at a high level, mobile robots are experiencing remarkable enhancements in hardware design, software performance, and connectivity advancements. In order to control Turtlebot 2, several algorithms have been developed using the Robot Operating System(ROS). However, ROS requires to be run on a high-cost computer which increases the hardware cost and the power consumption to the robot. Therefore, design an algorithm based on low-cost hardware is the most innovative way to reduce the unnecessary costs of the hardware, to increase the performance, and to decrease the power consumed by the computer on the robot. In this paper, we present a path-finding algorithm for TurtleBot 2 based on low-cost hardware. We implemented the algorithm using Raspberry pi, Windows 10 IoT core, and RPLIDAR A2. Firstly, we used Raspberry pi as the alternative to the computer employed to handle ROS and to control the robot. Raspberry pi has the advantages of reducing the hardware cost and the energy consumed by the computer on the robot. Secondly, using RPLIDAR A2 and Windows 10 IoT core which is running on Raspberry pi, we implemented the path-finding algorithm which allows TurtleBot 2 to navigate from the starting point to the destination using the map of the area. In addition, we used C# and Universal Windows Platform to implement the proposed algorithm.

• 전자공학회논문지A
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• 제32A권5호
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• pp.749-758
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• 1995

There are many testable design techniques, among which Scan path and BIST techniques are mainly used. In this paper, the increase of design effectiveness is discussed, when these techniques are applied to the practical implementation of chips. The following techniques are presented : 1) Blocks are commonly used to reduce test time without hardware increase, 2) MUX is used to implement the shortest Scan path, 3) Scan register is used which controls and/or observes several blocks to avoid the increase of hardware.

• 제어로봇시스템학회논문지
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• 제14권12호
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• pp.1238-1243
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• 2008

This paper presents an HILS(Hardware in the Loop Simulations) based experimental study for the UAV's flight trajectory planning/generation algorithms and guidance/control laws. For the various mission that is loaded on each waypoint, proper trajectory planning and generation algorithms are applied to achieve best performances. Specially, the 'smoothing path' generation and the 'tangent orbit path' guidance laws are presented for the smooth path transitions and in-circle loitering mission, respectively. For the control laws that can minimize the effects of side wind, side slip angle($\beta$) feedback to the rudder scheme is implemented. Finally, being implemented on real hardwares, all the proposed algorithms are validated with integrations of hardware and software altogether via HILS.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 D
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• pp.2249-2251
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• 2002

CATV Network management system of korea is used for mainly monitor forward broadcasting signal because of the difficulty of tracking. measuring and control reverse path noise. Thereby purpose of design of the hardware is removing return path noise of CATV Network for maintaining two way network service of the highest quality. Return path management system is very effective in making CATV Network be the best media for ultra high speed data communication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• 한국정보과학회논문지:시스템및이론
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• 제33권9호
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• pp.691-698
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• 2006

TCP/IP Offload Engine(TOE)는 TCP/IP 프로토콜을 네트워크 어댑터 상에서 처리함으로써 호스트 CPU의 프로토콜 처리 부하를 줄이는 기술이다. TOE의 구현 방안으로는 임베디드 프로세서를 사용한 소프트웨어 TOE, ASIC 기반의 하드웨어 TOE, 그리고 하드웨어와 소프트웨어 구현의 장점을 결합한 하이브리드 TOE 등이 제안되어 왔다. 본 논문에서는 하이브리드 방식의 TOE 구현을 위해 두 개의 프로세서 코어를 내장한 FPGA를 기반으로 임베디드 리눅스 기반의 소프트웨어 모듈 및 데이타 송수신에 필요한 하드웨어 모듈들을 설계하였다. 두 개의 프로세서 코어를 사용하여 송신 경로와 수신 경로를 분담하여 관리함으로써 리눅스 프로세스들 사이의 작업 전환 오버헤드를 줄일 수 있고, 송신과 수신 과정의 병렬 처리를 통해 단일 임베디드 프로세서의 성능 한계를 극복할 수 있다. 하드웨어 모듈은 패킷 헤더의 생성 및 처리, DMA를 사용한 데이타 수집 및 저장 등을 담당하여 송수신 성능을 향상시킨다. 본 논문에서는 프로세서 코어 내장형 FPGA가 장착된 TOE 네트워크 어댑터를 사용하여 송수신 분리형 TOE의 성능을 검증하였다.

• 한국정보통신학회논문지
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• 제8권3호
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• pp.570-576
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• 2004

본 논문에서는 고속 무선 LAN에서 사용하는 IEEE 802.11a OFDM(Orthogonal Frequency Division Multiplexing)에서 주요 구성인 IFFT/FFT(Inverse Fast Fourier Transform/Fast Fourier Transform)에 대한 설계에 대해 비교하였다. 설계된 IFFT/FFT는 무선 LAN의 표준에 맞게 64 point의 FFT로 연산을 수행하며, S/P(Serial-to-Parallel)이나 P/S(Parallel-to-Serial)변환기가 필요 없는 Pipelined FFT의 구조로 설계하였다. 그 중 Radix-2 알고리즘을 이용한 R22SDF(Radix-2 Single-path Delay Feedback) 방식, R2SDF(Radix-2 Single-path Delay Feedback) 방식과 Radix-4 알고리즘을 이용한 R4SDF(Radix-4 Single-path Delay Feedback) 방식, R4SDC(Radix-4 Single-path Delay Commutator) 방식을 사용하여 비교하였다. 하드웨어 구현 시 발생하는 오차를 줄이기 위해 Butterfly 연산 후 일부 소수점을 가지고 계산하는 구조로 설계하였다. R22SDF 방식을 이용할 경우 메모리를 제외한 전체 게이트 수가 44,747 개로 다른 구조에 비해 적은 하드웨어와 낮은 오차율을 가진다.