• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.485-492
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• 2003

This paper presents a new modified input buffered switch, which called a grouped input buffered (GIB) switch, to eliminate the influence of HOL blocking when using multiple input buffers in ATM switches. The GIB switch consists of grouped sub switches per a network stage. The switch gives extra paths and buffered switching elements between groups for transferring the blocked cells. As the result, the proposed model can reduce the effect by the HOL blocking and thereafter it enhances the performance of the switch. The simulation results show that the proposed scheme has good performance in comparison with previous works by using the parameters such as throughput, cell loss, delay and system power.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.319-326
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• 2001

본 논문에서는 다단계상호연결 네트워크에 기반한 입력버퍼 구조의 ATM 스위치에 관해서 언급한다. 제안된 방법은 HOL 블록킹으로 인해 균일 트래픽(uniform traffic) 하에서 최대 약 58.6%의 처리율을 넘지 못하는 문제를 해결 할 수 있는 방법을 제시하며, 또한 오류허용 기능을 확장시키기 위하여 베이스라인 네트워크에서 버디 연결 매핑 및 제한연결 매핑 특성을 이용한 다중경로를 제공할 수 있는 버퍼 기법에 관하여 언급한다. 시뮬레이션에 의한 성능 평가 결과, 기존 방식과 비교하여 좋은 처리율과 셀 손실율을 보였으며, 더욱이 오류 스위치의 증가에도 불구하고 처리율의 수준은 적정한 셀 지연 범위 내에서 유지될 수 있음을 보여주고 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.114-121
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• 2000

The problem of an input-buffered switch is the HOL(head-of-line) blocking which limits the maximum throughput but it is easy to implement in hardware. However, HOL blocking can be eliminated using aVOQ(virtual-output-queueing) technique. 0 this paper, we propose a new cell-scheduling algorithm for aninput-buffered ATM switch. The proposed algorithm, called PPIM(Probabilistic Parallel Iterative Matching), imposesa weight to every request based on the reserved bandwidth. It is shown that the input-buffered ATM switch withthe proposed PPIM algorithm not only provides high throughput and low delay but it also reduces the jitter,compared with the existing WPIM(Weighted PIM).

• Journal of the Korea Society of Computer and Information
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• v.8 no.2
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• pp.97-105
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• 2003

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The Proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output Port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms . The proposed switch acquires control over priority transmission through the REd signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the proposed switch under non-uniform random traffic conditions.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.115-123
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• 2002

This thesis proposes a new type of Input-Output Buffered ATM Switch which employs an arbiter and its performance under different traffic conditions studied. The proposed switch is designed with a view to exploit the architecture and other characteristics of the arbiter. The primary aim of the proposed switch is the elimination, or at least, the reduction of HOL blocking phenomenon which occurs in the simple input buffered switch. Several HOL arbitration algorithms have been proposed for this purpose in the literature. The proposed switch attempts to reduce the HOL blocking as it uses the arbiter and the buffer at the output port in an effective manner. The arbiter is designed to work with Three Phase Algorithm which is one of the many well known HOL arbitration algorithms. The Proposed switch acquires control over priority transmission through the REQ signal. As the signals are transmitted to the arbiter, the latter controls the one which is sent by the input buffer. Computer simulation results have been provided to demonstrate the effectiveness of the Proposed switch under uniform traffic conditions.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10b
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• pp.989-992
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• 2000

ATM 스위치로 많이 이용되는 다단계 상호연결 네트워크(MIN)는 self-routing 및 one-to-one 연결 특성을 가진 블록킹 네트워크로써 셀 전송시 충돌이 일어날 수 있다. 따라서 버퍼를 갖는 스위치를 고려하게 된다. 본 논문에서는 스위치의 내부에 다중경로를 제공하는 입력버퍼를 이용하여 각 스위치의 입력포트에서 출력포트로의 경로를 확장시킨 스위치 구조 및 네트워크의 성능 향상에 대하여 언급한다. 이를 위해 네트워크의 stage간 상호연결 패턴이 buddy 및 constrained reachability 특성에 따른 경로설정 구조를 기본으로 이용한다. 그리고 입력버퍼 스위치 구조의 문제점인 HOL 블록킹의 방지 및 오류허용 기능을 향상시킬 수 있는 다중경로 버퍼를 갖는 ATM 스위치 구조를 제안하고, 시뮬레이션을 통해 그 성능을 분석한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05a
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• pp.113-116
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• 2003

다단계 상호연결망(MIN)은 대규모 병렬처리 능력을 가지는 대표적 연결망 구조이다. 그러나 MIN은 입출력 사이의 단일경로와 블록킹 네트워크를 가지는 특성으로 인해 시스템 성능저하를 가져올 수 있다. 이러한 문제를 개선하기 위해 버퍼를 이용하거나 적은 하드웨어 추가와 스위치 대역폭 확장이 가능한 링크를 N배만큼 확장시키는 방법을 사용한다. 본 논문에서는 기존에 오류를 허용하기 위해 제안된 구조들보다 좀더 많은 오류를 허용하기 위한 방법으로 입력버퍼와 확장경로를 사용하여 HOL 블록킹을 방지하고 오류허용 기능을 향상시키는데 그 목적이 있다. 이에 따라 네트워크에 다중 오류가 발생하더라도 부하분산을 통해 이를 허용할 수 있는 구조를 제안하고 시뮬레이션을 통해 그 성능을 평가한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.473-476
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• 2001

본 논문에서는 HOL 블록킹 현상과 데드락을 줄이기 위해 공유 메모리 스위치를 이용하고 셀에 형태에 따라 유니캐스트 셀과 멀티캐스트 셀을 따로 저장하는 방법을 이용하여 셀의 부하를 줄이는 멀티캐스트 ATM 스위치를 제안한다. 그리고, 트래픽 셀의 손실을 줄이고, 효과적으로 출력하기 위해 제어부에서 출력 포트에 따라 스케줄링하는 기법을 택하였다. 제안한 스위치의 성능을 시뮬레이션을 통해 그 유효성을 보였다.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.169-175
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• 1998

There is a shared multibuffer method which can preventing HOL blocking in ATM switch. However, the system still has a problem that reduces the performance of the system because of the cell loss. Therefore, in this paper, preventing of cell loss in non-contentional shared multibuffer switch is suggested. To prevent cell loss, a structure is suggested that a cell can be loss in a certain slot time is stored in the dedicated temporary memory so the cell can be transferred in the next slot time. The simulation result of the structure, this suggested system superior performance than the exited system in cell loss rate and throughput.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.