• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.72-78
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• 2008

Although the H.264 video coding scheme is popular, it is not efficient for high-definition (HD) video coding because the size of its macroblock is relatively small for the HD video resolution. In this paper, we propose a new intra coding scheme based on the enlarged macroblock size. For the luminance component, intra $4{\times}4$ prediction and intra $16{\times}16$ prediction in H.264 are scaled into intra $8{\times}8$ prediction and intra $32{\times}32$ prediction, respectively. For the chrominance components, intra $8{\times}8$ prediction is extended to intra $16{\times}16$ prediction. Along with the $8{\times}8$ basic coding block size, an $8{\times}8$ integer discrete cosine transform (DCT) is used. Experimental results show that the proposed algorithm improves coding efficiency of the intra coding for HD video: PSNR gain by 0.23dB and bit-rate reduction by 5.32% on average.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.1-9
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• 2010

In this paper, the novel architecture of Intra-prediction & DCTQ hardware, which can process for the Full HD image($1980{\times}1088$@30fps) in realtime, is proposed. The cycle optimization method for the overall cycle of prediction, transform, scaling, descaling, and reconstruction is proposed. To reduce the cycle in the $4{\times}4$ prediction, the quantization process is performed during the prediction cycle and pre-selection of 2 modes among the 9 modes is performed to reduce the hardware area. To reduce the hardware of $16{\times}16$ and $8{\times}8$ prediction, the sharing logic between 2 prediction is utilized. The proposed architecture can process the 30frame/sec of full HD image in 108 MHz clock and operate 425 cycle for one macroblock.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.407-408
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• 2008

This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.43-53
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• 2010

Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

• Journal of Broadcast Engineering
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• v.15 no.2
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• pp.205-216
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• 2010

In this paper, a method of MPEG-2 Transport Stream (TS) multiplexing for Ultra HDTV (UHDTV) and its design and implementation as a SW tool is described. In practice, UHD video may be divided into several HD videos and each video is encoded in parallel. Therefore, it is necessary to synchronize and multiplex multiple bitstreams encoding each HD video for transmitting and storing UHD video. In this paper, it is assumed that 4 HD videos partitioning a UHD spatially are encoded as H.264/AVC and two 5.0 channel audios are encoded by AC-3. Therefore, 4 H.264/AVC elementary streams (ESs) and 2 AC-3 ESs is mainly considered in the TS multiplexing of UHD. For the carriage of H.264/AVC and AC-3 over MPEG-2 TS, PES packetization and TS multiplexing are designed and implemented based on the extended specification of the MPEG-2 Systems and ATSC (Digital audio compressed standard), respectively. The implemented UHD TS multiplexing tool emulates real time HW operation in the time unit corresponding to the duration of one TS packet transmission in a given TS rate. In particular, in order to satisfy the timing model, the buffers defined in the TS System Target Decoder (T-STD) are monitored and their statuses are considered in the scheduling of TS multiplexing. For UHD multiplexing, two kinds of multiplexing structures, which are UHD re-multiplexing and UHD program multiplexing, are implemented and their strength and weakness are investigated. The developed UHD TS multiplexing tool is tested and verified in terms of the syntax and semantics conformance and functionalities by using a commercial analyzer and real-time presentation tools.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.108-111
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• 2008

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder engine for real time Full HD video compression. Since there are 384 data coefficients which are sum of 376 AC coefficient and 8 DC coefficient per one macroblock, 384 coefficient have to be processed per one macroblock in worst case for real time processing. We propose an novel architecture which includes parallel architecture and pipeline processing, and reduction "0" in AC/DC coefficient table. To verify the proposed architecture, we develop the reference C for CAVLC and verified the designed circuit with the test vector from reference C code.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.2
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• pp.1-9
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• 2009

This paper develops a fast method performing intra prediction which only restores block boundary pixels without decoding all blocks in an I slice of H.264/AVC. To accomplish this, we develop a fast integer inverse DCT scheme that quickly decodes residual block boundary which can be consisted of references pixels. we add the restored block boundary pixels and appropriate calculated prediction pixels for each intra prediction mode and consist of needed reference pixels. The experiments showed that the proposed method produces the reliable performance with reducing the computational complexity, compared to conventional method when applied to H.264/AVC integer DCT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.64-70
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• 2008

The H.264 standard is widely used due to the high compression rate and quality. The deblocking filter of the H.264 standard improves the quality of images by eliminating blocking artifacts of pictures, and it requires a lot of computation. We propose a new hardware architecture for the deblocking filter with pipelined architecture, 1-D filters which support both horizontal and vertical filtering and efficient memory management. Four memory blocks are configured for the efficient storage and access of the current macroblock and adjacent referenced sub-macroblocks, and the pixel data from the motion compensation unit can be transferred without waiting during the computation cycles of the deblocking filter. The number of computation cycles and the hardware area are reduced using the proposed architecture, and the performance of the H.264 decoder is improved. We design the deblocking filter using Verilog-HDL and implement using an FPGA. The designed deblocking filter can be used for decoding HD quality images at 77 MHz.

• Journal of Broadcast Engineering
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• v.15 no.3
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• pp.434-453
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• 2010

In this paper, we propose 3DTE(3-Dimensional Transform Environment) that is based on 3DT(Dimensional Transform) that performs 2-dimensional integer DCT(Discrete Cosine Transform) based on $4{\times}4$ block and 1-dimensional integer DCT based on $4{\times}1$ block after collecting same frequency coefficients in neighboring $4{\times}4$ block and supports it's additional coding tools for high performance. The transform of 3DT can keep prediction error by using $4{\times}4$ block and reduce spatial redundancy additionally. The proposed 3DTE can provide coding tools to improve the coding efficiency with using 3DT. The performance of 3DTE compared to JM11.0 is average 3.58% and 5.40% bit savings for all test sequences and HD sequences, respectively, with keeping subjective video quality in High profile.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.187-191
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• 2009

This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD ($1,920{\times}1,088$) image frames per second at the maximum operating frequency of 101 MHz by using 130 nm standard cell library.