• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.58-65
• /
• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• ETRI Journal
• /
• v.29 no.1
• /
• pp.18-26
• /
• 2007

This paper presents an improved redundant picture coding method that efficiently enhances the error resiliency of H.264. The proposed method applies polyphase downsampling to residual blocks obtained from inter prediction and selectively encodes the rearranged residual blocks in the redundant picture coding process. Moreover, a spatial-temporal sample construction method is developed for the redundant coded picture, which further improves the reconstructed picture quality in error prone environments. Simulations based on JM11.0 were run to verify the proposed method on different test sequences in various error prone environments with average packet loss rates of 3%, 5%, 10%, and 20%. Results of the simulations show that the presented method significantly improves the robustness of H.264 to packet loss by 1.6 dB PSNR on average over the conventional redundant picture coding method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2010.11a
• /
• pp.175-177
• /
• 2010

본 논문에서는 MPEG 의 3차원 비디오 시스템의 표준 깊이정보 맵에 대한 효율적인 부호화를 위하여 전처리 방법을 제안한다. 현재 3차원 비디오 부호화(3DVC)에 대한 표준화가 진행 중에 있지만 아직 깊이정보 맵의 부호화 방법에 대한 표준이 확정되지 않은 상태이다. 제안하는 기법에서는 우선, 입력된 깊이정보 맵에 대하여 원래의 히스토그램 분포를 가우시안 혼합모델(GMM)기반의 EM 군집화 기법에 의한 방법으로 분리 후, 분리된 히스토그램을 기반으로 깊이정보 맵을 여러 개의 영상으로 분리한다. 그 후 분리된 각각의 영상을 배경과 객체에 따라 다른 조건의 mean shift filter로 필터링한다. 결과적으로 영상내의 각 영역 경계는 최대한 살리면서 영역내의 화소 값에 대해서는 평균 연산을 취하여 부호화시 효율을 극대화 하고자 하였다. 실험조건은 $1024{\times}768$ 영상에 대해서 50 프레임으로 H.264/AVC base 프로파일로 부호화를 진행하였다. 최종 실험결과 bit rate는 대략 23% ~ 26% 정도 감소하고 부호화 시간도 다소 줄어드는 것을 확인 할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.774-780
• /
• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.