• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of KIISE
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• v.44 no.9
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• pp.932-945
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• 2017

In this paper, a new hardware and software architecture for a stereo vision processing system including rectification, disparity estimation, and visualization was developed. The developed method, named LArge scale stereo matching method using Support Point Interpolation (LASPI), shows excellence in real-time processing for obtaining dense disparity maps from high quality image regions that contain high density support points. In the real-time processing of high definition (HD) images, LASPI does not degrade the quality level of disparity maps compared to existing stereo-matching methods such as Efficient LArge-scale Stereo matching (ELAS). LASPI has been designed to meet a high frame-rate, accurate distance resolution performance, and a low resource usage even in a limited resource environment. These characteristics enable LASPI to be deployed to safety-critical applications such as an obstacle recognition system and distance detection system for autonomous vehicles. A Field Programmable Gate Array (FPGA) for the LASPI algorithm has been implemented in order to support parallel processing and 4-stage pipelining. From various experiments, it was verified that the developed FPGA system (Xilinx Virtex-7 FPGA, 148.5MHz Clock) is capable of processing 30 HD ($1280{\times}720pixels$) frames per second in real-time while it generates disparity maps that are applicable to real vehicles.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.24.1-24.1
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• 2009

Tantalum carbo-nitride($T_aC_xN_y$) films were deposited with chemical vapor deposition(CVD) using tert-butylimido tris-diethylamido tantalum (TBTDET, $^tBu-N=Ta-(NEt_2)_3$, $Et=C_2H_5$, $^tBu=C(CH_3)_3$) between $350^{\circ}C$ and $600^{\circ}C$ with argon as a carrier gas. Fourier transform infrared (FT-IR)spectroscopy was used to study the thermal decomposition behavior of TBTDET in the gas phase. When the temperature was increased, C-H and C-N bonding of TBTDET disappeared and the peaks of ethylene appeared above $450^{\circ}C$ in the gas phase. The growth rate and film density of $T_aC_xN_y$ film were in the range of 0.1nm/min to 1.30nm/min and of $8.92g/cm^3$ to $10.6g/cm^3$ depending on the deposition temperature. $T_aC_xN_y$ films deposited below $400^{\circ}C$ were amorphous and became polycrystal line above $500^{\circ}C$. It was confirmed that the $T_aC_xN_y$ film was a mixture of TaC, graphite, $Ta_3N_5$, TaN, and $Ta_2O_5$ phases and the oxide phase was formed from the post deposition oxygen uptake. With the increase of the deposition temperature, the TaN phase was increased over TaC and $Ta_3N_5$ and crystallinity, work function, conductivity and density of the film were increased. Also the oxygen uptake was decreased due to the increase of the film density. With the increase of the TaC phase in $T_aC_xN_y$ film, the work function was decreased to 4.25eV and with the increase of the TaN phase in $T_aC_xN_y$ film,it was increased to 4.48eV.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Korean journal of applied entomology
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• v.4
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• pp.33-38
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• 1965

1. This survey was conducted to make a basis for the cause of severe epidemic and disease control to the losses due to bacterial leaf blight of rice in Chun-Nam rice paddy field areas in the first part of October in 1965. The severe epidemic areas were included Taijun-Myun, Tamyang-Eup, riverside in Youngsanpo and seaside in the suburbs of Mokpo. 2. A drought in the period of rice transplanting and flooding due to a heavy rain in July were resulted reasonable weather conditions that the disease occurred more early and severe epidemic. 3. In Tamyang area, frist outbreak of the disease was on the middle part of July in the paddy flooded after heavy rainfall of the first fart of July. It is recognized to farmers that the disease is known as a now serious one. 4. The more date of transplanting is followed, the more serious damage is happened and especially, in the paddy field flooded, too. 5. Flooded areas showed more serious epidemic. 6. Varietal difference to the disease was surely noticed, and Kumnampoong and Chunbonwuk were susceptible, whereas Norin 6 was resistant. 7. Damage was occurred more in plant paddy area than tile slopping paddy area. 8. Fallow paddy field was more serious than the field using double cropping a year. 9. Moist and semimoist paddy field were more serious damage, while light damage in dry paddy field. 10. Near part of flood gate for drainage of submerge paddy was more serious damage than inside part of the field. 11. Soft type is often seen in the mode of the disease occurrences. 12. The most farmers insisted that dropping water is caused to promote disease dissemination when disease occurred.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.35 no.4
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• pp.29-42
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• 2017

Jeongeuihyanggyo(旌義鄕校) is a kind of traditional, Confucian cultural landscapes that is located in Jeju special self-governing province. Its historical background illustrates that the first erection was started at Goseong-li of Seongsan-eup(城山邑 古城里) at Taejong(太宗) of 16 years(1417) and it moved to the west gate of Hyunseong(縣城) at Heojong(憲宗) of 15 years,(1849) Joseon. The aim at this study is to reveal characters of these Confucian Spatial Composition and Order, which are valuable resources that can be created into the cultural contents. The results demonstrate the characters of the Confucian cultural landscape as followings; the changing process of new building and its relocation, the utilization of antique maps in location interpretation of Jeongeuihyanggyo, Confucian symbolic elements of it, the spatial compositions and layouts of its buildings, physical structures, main buildings and their characters, locational points of topographic profile, changes of axial line at Daeseongjeon(大成殿), the D/H ratio of its courts. This study can show that Jeongeuihyanggyo is a case for realizing the Confucian reformation to enhance Seongeup Hyun's education standard considering the locality of the site which is an isolated island like Jejudo(濟州島). The author can see that the example of Confucian space is applied to various layout techniques, both horizontally and vertically, in a limited space condition of being in the castle. Therefore, it is necessary to revive this point so that it can utilize unique Confucian cultural landscape possessed only by Jeongeuihyanggyo.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2003.09a
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• pp.44-44
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• 2003

As a basic measurement tool in the areas of animal models of human disease, gene expression and therapy, and drug discovery and development, small animal PET imaging is being used increasingly. An ideal small animal PET should have high sensitivity and high and uniform resolution across the field of view to achieve high image quality. However, the combination of long narrow pixellated crystal array and small ring diameter of small animal PET leads to the degradation of spatial resolution for the source located at off center. This degradation of resolution can be improved by determining the depth of interaction (DOI) in the crystal and by taking into account the information in sorting the coincident events. Among a number of 001 identification schemes, dual layer phsowich detector has been widely investigated by many research groups due to its practicability and effectiveness on extracting DOI information. However, the effects of each crystal length composing dual layer phoswich detector on DOI measurements and image qualities were not fully characterized. In order to minimize the DOI effect, the length of each layer of phoswich detector should be optimized. The aim of this study was to perform simulations using a simulation tool, GATE to design the optimum lengths of crystals composing a dual layer phoswich detector. The simulated small PET system employed LSO front layer LuYAP back layer phoswich detector modules and the module consisted of 8${\times}$8 arrays of dual layer crystals with 2 mm ${\times}$ 2 mm sensitive area coupled to a Hamamatsu R7600 00 M64 PSPMT. Sensitivities and variation of radial resolutions were simulated by varying the length of LSO front layer from 0 to 10 mm while the total length (LSO + LuYAP) was fixed to 20 mm for 10 cm diameter ring scanner. The radial resolution uniformity was markedly improved by using DOI information. There existed the optimal lengths of crystal layers to minimize the variation of radial resolutions. In 10 cm ring scanner configuration, the radial resolution was kept below 3.4 mm over 8 cm FOV while the sensitivity was higher than 7.4% for LSO 5 mm : LuYAP 15 mm phoswich detector. In this study, the optimal length of dual layer phoswich detector was derived to achieve high and uniform radial resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.327-332
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• 2011

Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.