• Title/Summary/Keyword: Graphics processing unit(GPU)

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Research on the Development of an Integral Imaging System Framework and an Improved Viewpoint Vector Rendering Method Utilizing GPU (GPU를 이용한 개선된 뷰포인트 벡터 렌더링 방식의 집적영상시스템 프레임워크에 관한 연구)

  • Lee, Bin-Na-Ra;Park, Kyoung-Shin;Cho, Yong-Joo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.10
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    • pp.1767-1772
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    • 2006
  • Computer-generated integral imaging system is an auto-stereoscopic display system that users can see and feel the stereoscopic images when they see the pre-rendered elemental images through a lens array. The process of constructing elemental images using computer graphics is called image mapping. Viewpoint vector rendering (VVR) method is one of the image mapping algorithm specially designed for real-time graphics applications, which would not be affected by the size of the rendered objects or the number of elemental lenses used in the integral imaging system. This paper describes a new VVR framework which improved its rendering performance considerably. It also compares the previous VVR implementation with the new VVR work utilizing GPU and shows that newer implementation shows pretty big improvements over the old method.

Real-time Stereo Video Generation using Graphics Processing Unit (GPU를 이용한 실시간 양안식 영상 생성 방법)

  • Shin, In-Yong;Ho, Yo-Sung
    • Journal of Broadcast Engineering
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    • v.16 no.4
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    • pp.596-601
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    • 2011
  • In this paper, we propose a fast depth-image-based rendering method to generate a virtual view image in real-time using a graphic processor unit (GPU) for a 3D broadcasting system. Before the transmission, we encode the input 2D+depth video using the H.264 coding standard. At the receiver, we decode the received bitstream and generate a stereo video using a GPU which can compute in parallel. In this paper, we apply a simple and efficient hole filling method to reduce the decoder complexity and reduce hole filling errors. Besides, we design a vertical parallel structure for a forward mapping process to take advantage of the single instruction multiple thread structure of GPU. We also utilize high speed GPU memories to boost the computation speed. As a result, we can generate virtual view images 15 times faster than the case of CPU-based processing.

Construction and Rendering of Trimmed Blending Surfaces with Sharp Features on a GPU

  • Ko, Dae-Hyun;Lee, Ji-Eun;Lim, Seong-Jae;Yoon, Seung-Hyun
    • ETRI Journal
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    • v.33 no.1
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    • pp.89-99
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    • 2011
  • We construct surfaces with darts, creases, and corners by blending different types of local geometries. We also render these surfaces efficiently using programmable graphics hardware. Points on the blending surface are evaluated using simplified computation which can easily be performed on a graphics processing unit. Results show an eighteen-fold to twenty-fold increase in rendering speed over a CPU version. We also demonstrate how these surfaces can be trimmed using textures.

An IPC-based Dynamic Cooperative Thread Array Scheduling Scheme for GPUs

  • Son, Dong Oh;Kim, Jong Myon;Kim, Cheol Hong
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.2
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    • pp.9-16
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    • 2016
  • Recently, many research groups have focused on GPGPUs in order to improve the performance of computing systems. GPGPUs can execute general-purpose applications as well as graphics applications by using parallel GPU hardware resources. GPGPUs can process thousands of threads based on warp scheduling and CTA scheduling. In this paper, we utilize the traditional CTA scheduler to assign a various number of CTAs to SMs. According to our simulation results, increasing the number of CTAs assigned to the SM statically does not improve the performance. To solve the problem in traditional CTA scheduling schemes, we propose a new IPC-based dynamic CTA scheduling scheme. Compared to traditional CTA scheduling schemes, the proposed dynamic CTA scheduling scheme can increase the GPU performance by up to 13.1%.

Design of a SIMT architecture GP-GPU Using Tile based on Graphic Pipeline Structure (타일 기반 그래픽 파이프라인 구조를 사용한 SIMT 구조 GP-GPU 설계)

  • Kim, Do-Hyun;Kim, Chi-Yong
    • Journal of IKEEE
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    • v.20 no.1
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    • pp.75-81
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    • 2016
  • This paper proposes a design of the tile based on graphic pipeline to improve the graphic application performance in SIMT based GP-GPU. The proposed Tile based on graphics pipeline avoids unnecessary graphic processing operation, and processes the rasterization step in parallel. The massive data processing in parallel through SIMT architecture improve the computational performance, thereby improving the 3D graphic pipeline performance. The more vertex data of 3D model, the higher performance. The proposed structure was confirmed to improve processing performance of up to 3 times from about 1.18 times as compared to 'RAMP' and previous studies.

IPC-based Dynamic SM management on GPGPU for Executing AES Algorithm

  • Son, Dong Oh;Choi, Hong Jun;Kim, Cheol Hong
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.2
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    • pp.11-19
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    • 2020
  • Modern GPU can execute general purpose computation on the graphic processing unit, and provide high performance by exploiting many core on GPU. To run AES algorithm efficiently, parallel computational resources are required. However, computational resource of CPU architecture are not enough to cryptographic algorithm such as AES whereas GPU architecture has mass parallel computation resources. Therefore, this paper reduce the time to execute AES by employing parallel computational resource on GPGPU. Unfortunately, AES cannot utilize computational resource on GPGPU since it isn't suitable to GPGPU architecture. In this paper, IPC based dynamic SM management technique are proposed to efficiently execute AES on GPGPU. IPC based dynamic SM management can increase and decrease the number of active SMs by using IPC in run-time. According to simulation results, proposed technique improve the performance by increasing resource utilization compared to baseline GPGPU architecture. The results show that AES improve the performance by 41.2% on average.

An Optimization for fast digital hologram generation based on GPU (GPU기반의 디지털 홀로그램 고속 생성을 위한 최적화 기법)

  • Song, Joong-Seok;Park, Jong-Il
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2011.07a
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    • pp.18-21
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    • 2011
  • 디지털 홀로그램은 일반적으로 computer generated hologram(CGH)기법에 의해서 생성된다. 하지만 원리적으로 CGH 기법은 많은 연산량과 복잡도를 요구하고 있기 때문에 실시간으로 디지털 홀로그램을 생성하는 것은 매우 어렵다. 본 논문에서는 CGH 고속연산을 위해 graphics processing unit(GPU)의 병렬처리구조인 CUDA를 사용하였고, 추가적으로 다중 GPU 연산처리를 위해 OpenMP를 사용하였다. 더 나아가 이를 최적화하기 위해서 상수화, 벡터화, 루프풀기 등의 기법들을 제안한다. 결과적으로, 본 논문에서 제안된 기법을 통해서 기존 CPU에서의 CGH 연산속도에 비해 약 8,300배 정도의 속도를 개선할 수 있었다.

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Trends of Hardware Acceleration Technology in Wed Browser (HW 가속 기반 웹 고속화 기술동향)

  • Lee, J.H.;Cho, H.W.;Kim, D.H.;Lee, H.S.;Yoon, S.J.;Ryu, C.;Cho, C.S.
    • Electronics and Telecommunications Trends
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    • v.31 no.4
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    • pp.65-76
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    • 2016
  • 특정 제조사의 단말 또는 운영체제에 의존성이 없는 플랫폼 독립적인 웹은 높은 이식성, 소프트웨어의 재활용, 개발 생산성, 풍부한 개발자 존재, 유지 보수 면에서 장점을 가지나, 화려한 UI/UX를 제공하는 네이티브 응용에 비해 낮은 성능으로 웹 기반의 응용 개발 및 보급이 크게 활성화되지 못했다. 한편 데스크톱은 물론 모바일 단말의 멀티코어 기반 Graphic Processing Unit(GPU), CPU 탑재 등 HW 고사양화와 웹 응용에서도 HW 가속 기능을 활용할 수 있는 표준 제공으로 성능 제약을 극복할 수 있게 되었다. 본고에서는 GPU 발전동향을 살펴보고, 고속 렌더링 및 병렬 연산처리를 요구하는 웹 응용이 GPU기반 HW 가속 기능을 활용할 수 있는 크로노스 그룹의 그래픽 가속(Web Graphics Library: WebGL) 및 컴퓨팅(Web Computing Language: WebCL) 지원 표준 규격을 정리한다. 또한, 최근 차세대 GPU Application Programming Interface(API)로 발표된 Vulkan에 대해 알아보고, 웹 고속화 기술에 적용 가능성에 대해 전망한다.

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BCDR algorithm for network estimation based on pseudo-likelihood with parallelization using GPU (유사가능도 기반의 네트워크 추정 모형에 대한 GPU 병렬화 BCDR 알고리즘)

  • Kim, Byungsoo;Yu, Donghyeon
    • Journal of the Korean Data and Information Science Society
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    • v.27 no.2
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    • pp.381-394
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    • 2016
  • Graphical model represents conditional dependencies between variables as a graph with nodes and edges. It is widely used in various fields including physics, economics, and biology to describe complex association. Conditional dependencies can be estimated from a inverse covariance matrix, where zero off-diagonal elements denote conditional independence of corresponding variables. This paper proposes a efficient BCDR (block coordinate descent with random permutation) algorithm using graphics processing units and random permutation for the CONCORD (convex correlation selection method) based on the BCD (block coordinate descent) algorithm, which estimates a inverse covariance matrix based on pseudo-likelihood. We conduct numerical studies for two network structures to demonstrate the efficiency of the proposed algorithm for the CONCORD in terms of computation times.

An Analytical Model for Performance Prediction of AES on GPU Architecture (GPU 아키텍처의 AES 암호화 성능 예측 분석 모델)

  • Kim, Kyuwoon;Kim, Hyunwoo;Kim, Huijeong;Huh, Taeyoung;Jung, Sanghyuk;Song, Yong Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.4
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    • pp.89-96
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    • 2013
  • The graphic processor unit (GPU) has been developed to process not only graphic data but also general system data. It shows a better performance than CPU in algorithm for 3D graphics and parallel program. In order to execute algorithm for CPU on GPU, we should understand about GPU architectures and rewrite program considering parallel processing capability and new memory model of GPU. For this reasons, a performance prediction model for the algorithm and its predicted performance through GPU system are required. These can predict problems in GPU application development or construct a performance evaluation standard for GPU. In this paper, we applied the AES encryption algorithms on our performance model and accomplished performance prediction with high accuracy under a heavy workload.