• 한국재료학회지
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• 제16권9호
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.

• 한국재료학회지
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• 제16권9호
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• 한국진공학회지
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• 제5권1호
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• pp.39-47
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• 1996

The segregation of S in electrotransport-purified polycrystaline $\alpha$-Ti and Ti-aluminide alloys has been studied by Auger electron spectroscopy(AES), Ion scattering spectroscopy(ISS) and Secondary ion mass spectrometry(SIMS) in the temperature range extending from 20 to $1000^{\circ}C$. The chemisorbed oxygen and carbon on Ti were observed to disappear at T>$400^{\circ}C$ after which the S signal increased to levels approaching 0.5 monolayer. At lower temperatures the presence of the surface oxygen and carbon appeared to inhibit the segregation, presumably because there were no available surfaces sites for the S emerging from the bulk. The activation energy for the S segregation in pure polycrystaline Ti was determined to be 16.7 kcal/mol, which, when compared to S segretation from single-crystal Ti, is quite small and suggests grain boundary or defect diffusion segregation kinetics. In the Ti-aluminide alloys, the presence of Al appeared to enhance the retention of surface oxygen which, in turn, substantially reduced the S segretation. The $\gamma$ alloy, with its high Al content, exhibited the greatest retention of surface oxygen and the smallest quantity of the S segregation(T$\simeq1000^{\circ}C$).

• 한국분말재료학회지
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• 제31권2호
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• pp.146-151
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• 2024

Pure SnO₂ has proven very difficult to densify. This poor densification can be useful for the fabrication of SnO₂ with a porous microstructure, which is used in electronic devices such as gas sensors. Most electronic devices based on SnO₂ have a porous microstructure, with a porosity of > 40%. In pure SnO₂, a high sintering temperature of approximately 1300℃ is required to obtain > 40% porosity. In an attempt to reduce the required sintering temperature, the present study investigated the low-temperature sinterability of a current system. With the addition of TiO₂, the compositions of the samples were Sn_1-xTi_xO₂-CoO(0.3wt%)-CuO(2wt%) in the range of x ≤ 0.04. Compared to the samples without added TiO₂, densification was shown to be improved when the samples were sintered at 950℃. The dominant mass transport mechanism appears to be grain-boundary diffusion during heat treatment at 950℃.

• 한국재료학회지
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• 제1권3호
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• pp.125-131
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• 1991

pMOS소자의 $p^{+}$게이트 전극으로 다결정실리콘과 비정질실리콘을 사용하여 고온의 열처리 공정에 따른 붕소이온의 침투현상을 high frequency C-V plot, Constant Current Stress Test(CCST), Secondary Ion Mass Spectroscopy(SIMS) 및 Transmission Electron Microscopy(TEM)를 이용하여 비교하였다. C-V plot분석 결과 비정질실리콘 게이트가 다결정실리콘 게이트에 비해 flatband전압의 변화가 작게 나타났으며, 게이트 산화막의 절연파괴 전하밀도에서는 60~80% 정도 향상된 값을 나타내었다. 비정질실리콘 게이트는 증착시 비정질로 형성되는 구조로 인한 얇은 이온주입 깊이와 열처리 공정시 다결정실리콘에 비교하여 크게 성장하는 입자 크기 때문에 붕소이온의 침투 경로가 되는 grain boundary를 감소시켜 붕소이온 확산을 억제한 것으로 생각된다. Electron trapping rate와 flatband 전압 변화와의 관계에 대하여 고찰하였다.

• 한국진공학회지
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• 제12권3호
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• pp.174-181
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• 2003

본 논문은 탄탈 확산 방지막의 증착시 음의 기판 바이어스에 의한 탄탈막의 특성변화와 열적 안정성에 대해서 고찰하였다. 기판 바이어스를 걸지 않은 경우, 탄탈막은 원주형 모양의 결정 성장을 보이는 주상구조와 250 $\mu\Omega$cm의 높은 비저항값을 보였으나, 기판 바이어스를 걸어줌에 파라서 주상구조가 아닌 치밀한 미세구조와 표면이 평탄한 막이 형성되었고 비저항값도 현저히 감소되었으며, 특히 -125 V에서 증착된 탄탈막은 비저항값이 약 40 $\mu\Omega$cm로 이는 탄탈 벌크의 저항값 (13 $\mu\Omega$cm)에 근접한 값임을 알 수 있었다. 또한, 탄탈 확산 방지막의 열적 안정성에 대해서도, 기판 바이어스를 걸지 않은 탄탈막의 경우 $400^{\circ}C$에서 구리와 실리콘의 반응에 의해 비저항 값이 크게 증가한 결과에 비해, 기판 바이어스에 의해 증착된 탄탈막의 경우 $600^{\circ}C$까지 확산 방지막의 효과를 유지하고 있는 것으로 관찰되었다.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1997년도 춘계학술발표회논문집(2)
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• pp.165-170
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• 1997

Samples of extruded dispersions of 24 vol.% spherical U-2wt%Mo and U-10wt.%Mo powders in an aluminum matrix were annealed for over 2,000 hours at 40$0^{\circ}C$. No significant dimensional changes occurred in the U-1025.%Mo/aluminum dispersions. The U-2wt.%Mo/aluminum dispersion, however, increased in volume by 26% after 2,000 hours at 40$0^{\circ}C$. This large volume change is mainly due to the formation of voids and cracks resulting from nearly complete interdiffusion of U-Mo and aluminum. Interdiffusion between U-10wt.%Mo and aluminum was found to be minimal. The different diffusion behavior is primarily due to the fact that U-2wt.%Mo decomposes from an as-atomized metastable r-phase(bcc) solid solution into the equilibrium r-U and U$_2$Mo two-phase structure during the experiment, whereas U-10wt.%Mo retains the metastable r-phase structure after the 2,000 hours anneal and thereby displays superior thermal compatibility with aluminum compared to U-2wt.%Mo. In addition, the molybdenium supersaturated in U-10wt.%Mo particles inhibits the diffusion of aluminum atoms along the grain boundary into the particle. Also, the dissolution of only a few Mo atoms in UAL$_3$ retards the formation of the intermediate phase, as Mo atoms need to migrate from new intermetallic compounds to unreacted islands.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 방사성폐기물학회지
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• 제5권1호
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• pp.39-52
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• 2007

사용후핵연료의 건식 재가공을 위한 핵연료 원격 제조공정중 분말제조를 위한 산화 및 OREOX(산화 환원공정)열처리 공정으로부터 $^{85}Kr$ 및 $^{14}C$ 핵분열기체의 방출거동을 정량적으로 평가하였다. 특히 사용후핵연료의 평균 연소도가 $27,000{\sim}65,000\;MWd/tU$ 범위내에서 연소도 변화에 따른 핵분열기체의 방출 분율은 측정한 실험결과와 ORIGEN 코드로부터 계산된 초기 inventory를 상호 비교하여 구하였다. $500^{\circ}C$ 1차 산화공정(voloxidation)에서 $^{85}Kr$ 및 $^{14}C(^{14}CO_2)$의 시간에 따른 방출거동은 $UO_2$ 핵연료의 $U_3O_8$으로의 분말화 정도와 밀접한 관련이 있는 것으로 보이며, 입계(grain-boundary)에 분포된 핵분열기체가 대부분 방출되는 것으로 여겨진다. 산화분말을 이용한 OREOX 공정으로부터 핵분열기체의 높은 방출율은 $700^{\circ}C$의 환원공정에서 온도 증가에 의한 기체 확산 및 $UO_2$으로의 환원에 의한 U 원자 이동성 증가에 의존하며 주로 inter-grain 및 intra-grain에 분포된 핵분열기체가 방출된 것으로 판단된다. 일차 산화공정시 $^{85}Kr$ 및 $^{14}C$ 핵분열기체의 방출 분율은 핵 연료 연소도가 증가함에 따라 높게 나타났고 방출 분율 범위는 총 inventory의 $6{\sim}12%$정도며, 산화분말의 OREOX 공정처리시 잔류 핵분열기체 대부분이 방출되는 것으로 보인다. 아울러 사용후핵 연료로부터 핵분열기체의 제거를 위해서는 고온 환원분위기보다는 산화에 의한 분말화가 더 효과적인 것으로 여겨진다.

• 한국자기학회지
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• 제12권2호
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• pp.41-45
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• 2002

졸-겔법으로 제조된 La/sub 0.7/Pb/sub 0.3/MnO₃(LPM)박막의 기판 효과에 따른 저 자장 영역에서의 터널형 자기저항 효과에 대하여 연구하였다. 다결정 LPMO 박막은 SiO₂/Si(100) 기판과 그 위에 확산 방지막(diffusion barrier)으로 안정화 지르코니아(yttria-stabilized zirconia, YSZ) 중간층을 도입한 기판에 증착하였으며, 반면에 c-축 방향 성장을 갖는 박막의 경우 LaA1O₃(001) (LAO) 단결정 기판을 사용하였다. LPMO/LAO 박막에서의 rocking curve 측정 결과 full width half maximum (FWHM) 값은 0.32°값을 가짐을 알 수 있었다. 상온(300 K)에서 측정한 자기저항비(MR ratio) 값은 500 Oe리 외부자장을 인가시 LPMO/SiO₂/Si 박막의 경우 0.52%, LPMO/YSZ/SiO₂/Si 박막인 경우는 0.68% 그리고, LPMO/LAO의 경우에는 0.4%에도 미치지 못하는 값을 가졌다. 이때 MR최대값을 나타내는 peaks는 자기이력 곡선의 보자력 부근에서 나타남으로 그 두 결과가 잘 일치함을 보여 주고 있다. 이러한 저 자장 영역에서의 자기저항 값의 타이는 박막 시료의 기판 효과에 의한 grain boundary특성의 차이로부터 기인된다.