• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.4
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• pp.267-273
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• 1998

The band structures of $Si_{1-x}Ge_x$ layers grown on $Si_{1-y}Ge_y$ substrate are calculated using k$\cdot$p and strain Hamiltonians. The hole drift mobilities in the plane direction are then calculated by taking into account the screening effect and the density-of-states of the impurity band. When $Si_{1-x}Ge_x$ is grown on Si substrate, the mobilities of (110) and (111) $Si_{1-x}Ge_x$ layers are larger than that of (001) $Si_{1-x}Ge_x$. However, due to the large defect and surface scattering, (110) and (111) $Si_{1-x}Ge_x$ layers may not be useful for the development of the fast device. Meanwhile, when Si is grown on $Si_{1-y}Ge_y$ substrate, the mobilities of (001) and (110) Si layers are greatly enhanced. Based on the amount of defect and the surface scattering, it is expected that Si grown on (001) $Si_{1-y}Ge_y$ substrate, where the Ge contents is larger than 10%(y>0.1), has the highest mobility.

• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.346-352
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• 2000

We investigated the oxidation behavior of poly $Si_{1-x}Ge_x$ films (X=0.15, 0.42) at $700^{\circ}C$ in wet oxidation ambients and analyzed the oxide by XPS, RBS, and cross-sectional TEM. In the case of poly $Si_{0.85}Ge_{0.15}$ films, $SiO_2$ was formed on the poly $Si_{1-x}Ge_x$ films and Ge was rejected from growing oxide, subsequently leading to the increase of Ge content. In the case of poly $Si_{0.58}Ge_{0.42}$ films, we found that $SiO_2-GeO_2$ were formed on the poly $Si_{1-x}Ge_x$ films due to high Ge content. Finally, we proposed the oxidation model of poly $Si_{1-x}Ge_x$ films.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1672-1678
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• 1989

Major problems preventing the device-quality GaAs/Si heterostructure are the lattice mismatch of about 4% and difference in thermal expansion coefficient by a factor of 2.64 between Si and GaAs. Ge is a good candidate for the buffer layer because its lattice parameter and thermal expansion coefficient are almost the same as those of GaAs. As a first step toward developing heterostructure such as GaAs/Ge/Si entirely by a home-built PAE (plasma-assisted epitaxy), Ge films have been deposited on p-type Si (100)substrate by the plasma assisted evaporation of solid Ge source. The characteristics of these Ge/Si heterostructure were determined by X-ray diffraction, SEM and Auge electron spectroscope. PAE system has been successfully applied to quality-good Ge layer on Si substrate at relatively low temperature. Furthermore, this system can remove the native oxide(SiO2) on Si substrate with in-situ cleaning procedure. Ge layer grown on Si substrate by PAE at substrate temperature of 450\ulcorner in hydrogen partial pressure of 10mTorr was expected with a good buffer layer for GaAs/Ge/Si heterostructure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.44-48
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• 2008

Hole mobility characteristics of two representative biaxially strained SiGe/Si structures with high Ge contents are studied, They are single channel ($Si/Si_{1-x}Ge_x/Si$ substrate) and dual channel ($Si/Si_{1-y}Ge_y/Si_{1-x}Ge_x/Si$ substrate), where the former consists of a relaxed SiGe buffer layer with 60 % Ge content and a tensile-strained Si layer on top, and for the latter, a compressively strained SiGe layer is inserted between two layers, Owing to the hole mobility performance between a relaxed SiGe film and a compressive-strained SiGe film in the single channel and the dual channel, the hole mobility behaviors of two structures with respect to the Si cap layer thickness shows the opposite trend, Hole mobility increases with thicker Si cap layer for single channel structure, whereas it decreases with thicker Si cap layer for dual channel. This hole mobility characteristics could be easily explained by a simple capacitance model.

• Journal of the Korean Ceramic Society
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• v.37 no.5
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• pp.432-437
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• 2000

Thermoelectric properties of p-type SiGe alloys prepared by a RF inductive furnace were investigated. Non-doped Si80Ge20 alloys were fabricated by control of the quantity of volatile Ge. The carrier of p-type SiGe alloy was controlled by B-doping. B doped p-type SiGe alloys were synthesized by melting the mixture of Ge and Si containing B. The effects of sintering/annealing conditions and compaction pressure on thermoelectric properties (electrical conductivity and Seebeck coefficient) were investigated. For nondoped SiGe alloys, electrical conductivity increased with increasing temperatures and Seebeck coefficient was measured negative showing a typical n-type semiconductivity. On the other hand, B-doped SiGe alloys exhibited positive Seebeck coefficient and their electrical conductivity decreased with increasing temperatures. Thermoelectric properties were more sensitive to compaction pressure than annealing time. The highest power factor obtained in this work was 8.89${\times}$10-6J/cm$.$K2$.$s for 1 at% B-doped SiGe alloy.

• ETRI Journal
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• v.25 no.4
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• pp.247-252
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• 2003

This paper presents results from experiments on laser-annealed SiGe-selective epitaxial growth (LA-SiGe-SEG). The SiGe-SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA-SiGe-SEG technique with highly doped Ge and an ultra shallow junction on p-type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA-SiGe-SEG technology is suitable for fabricating high-speed, low-power devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.573-578
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• 2003

Low temperature selective epitaxial growth of Si and SiGe has been obtained using an industrial single wafer chemical vapor deposition module operating at reduced pressure. Epitaxial Si and heteroepitaxial SiGe deposition with Ge content about 20 % has been studied as extrinsic base for self-aligned heterojunction bipolar transistors(HBTs), which helps to reduce the parasitic resistance to obtain higher maximum oscillation frequencies(f$\_$max/). The dependence of Si and SiGe deposition rates on exposed windows and their evolution with the addition of HCl to the gas mixture are investigated. SiH$_2$Cl$_2$ was used as the source of Si SEG(Selective Epitaxial Growth) and GeH$_4$ was added to grow SiGe SEG. The addition of HCl into the gas mixture allows increasing an incubation time even low growth temperature of 675∼725$^{\circ}C$. In addition, the selectivity is enhanced for the SiGe alloy and it was proposed that the incubation time for the polycrystalline deposit on the oxide is increased probably due to GeO formation. On the other hand, when only SiGe SEG(Selective Epitaxial Growth) layer is used for extrinsic base, it shows a higher sheet resistance with Ti-silicide because of Ge segregation to the interface, but in case of Si or Si/SiGe SEG layer, the sheet resistance is decreased up to 70 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.1-7
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• 2004

In order to enhance the electron mobility in SOI n-MOSFET, we fabricated fully depletion(FD) n-MOSFET on the strained Si/relaxed SiGa/SiO$_2$/Si structure(strained Si/SGOI) formed by inserting SiGe layer between a buried oxide(BOX) layer and a top silicon layer. The summated thickness of the strained Si and relaxed SiGe was fixed by 12.8 nm and then the dependency of electron mobility on strained Si thickness was investigated. The electron mobility in the FD n-MOSFET fabricated on the strained Si/SGOI enhanced about 30-80% compared to the FD n-MOSFET fabricated on conventional SOI. However, the electron mobility decreased with the strained Si thickness although the inter-valley phonon scattering was reduced via the enhancement of the Ge mole fraction. This result is attributed to the increment of intra-valley phonon scattering in the n-channel 2-fold valley via the further electron confinement as the strained Si thickness was reduced.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.4
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• pp.578-588
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• 1997

Poly-$Si_{1-x}Ge_x$ films on oxidized Si wafer were prepared by rapid thermal chemical vapor deposition using the $SiH_4$ and $GeH_4$ gaseous mixture at various deposition conditions. The deposition temperature, $SiH_4\;: GeH_4$ flow ratio and pressure were varied from 400 to $600^{\circ}C$, 1 : 0.1-2 : 1 and 1 to 50 torr, respectively. In this work, we have investigated the change of Ge composition of poly-$Si_{1-x}Ge_x$ films deposited with the variation of deposition parameters and the effect of Ge composition on the deposition rate. From the experimental results, it was observed that the deposition rate increased with increasing deposition temperature and Ge composition. On the other hand, the Ge composition decreased with increasing temperature. As the deposition pressure increased, the deposition rate and Ge composition were increased linearly to 10 torr but increased slowly above it, which has been attributed to the slower rate of surface reaction than mass transfer.