• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.185-188
• /
• 2001

In this study, $Al_2$O$_3$films have been deposited with Atomic Layer Deposition(ALD) for gate insulator for MPTMA and $H_2O$ at low temperature below 40$0^{\circ}C$ . Conventional methods of $Al_2$O$_3$thin film deposition have suffered from the poor step coverage due to reduction of device dimension and increasing contact/via hole aspect ratio. ALD is a self-limiting growth process with controlled surface reaction where the growth rate is only dependent on the number of growth cycle and the lattice parameter of materials. ALD growth process has many advantages including accurate thickness control, large area and large batch capability, good uniformity, and pinholes freeness.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.381-384
• /
• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.228-231
• /
• 1999

This paper describes the design and implementation of an application specific instruction-set processor developed for embedded DSP applications. The instruction-set has an uniform size of 16 bits, and supports 3 types of instructions: Primitive, Complex, and Specific. To reduce code size and cycle count we introduce complex instructions that can be selected according to the application under consideration, which leads to 50% code size reduction maximally. The processor has two independent data memories to double the data throughput and the address space. The processor is synthesized by 0.6$\mu$m single-poly double-metal technology. Critical path simulation shows that the maximum frequency is 110MHz and total gate count is 132, 000.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
• /
• 1997.10a
• /
• pp.3-8
• /
• 1997

본 연구에서는 복합발전시스템의 외기온도 변화로 인한 출력저하 문제를 극복할 수 있는 LNG 냉열 이용 복합발전 시스템을 제안하였다. 본 연구에 의해 제안된 LNG 냉열 이용 복합발전 시스템의 타당성을 검토하기 위해 ASPEN과 GateCycle을 이용한 시뮬레이션 모델을 구성하였고, 모델에 의해 예측한 결과를 실제 발전소 성능시험결과와 비교하여, 본 시뮬레이션 방법의 예측정확도를 검증하였다. 본 시뮬레이션 방법을 토대로 LNG 냉열을 이용하여 가스터빈의 유입공기를 냉각시켰을 경우의 복합발전 시스템 성능변화를 분석하였다. 그 결과 LNG 냉열을 이용하여 유입 공기를 원하는 온도까지 냉각시켜 하절기에도 출력을 일정하게 유지시킬 수 있음을 확인할 수 있었고, 이를 위한 기스터빈과 LNG 간의 열교환기 설계기준도 제시하였다.

• Journal of IKEEE
• /
• v.18 no.4
• /
• pp.630-635
• /
• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.332-333
• /
• 2018

This paper presents an advanced abnormal over-current protection with $SuperFET^{(R)}$ 800V MOSFET in Flyback converter. In advanced abnormal over-current protection, digital pattern generator is proposed to detect a steep di/dt current condition when secondary rectifier diode or the transformer is shorted. If current sensing signal is larger than current limit during consecutive switching cycle, Gate signal will be stopped for 7 internal switching periods. If the abnormal over-current maintains pattern, the controller goes into protection mode. The Advanced over-current protection has been implemented in a 0.35um BCDMOS process (ON Semiconductor process).

• ETRI Journal
• /
• v.34 no.2
• /
• pp.284-287
• /
• 2012

Quantum-dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA-based circuits.

• Journal of the Korean Vacuum Society
• /
• v.11 no.4
• /
• pp.230-234
• /
• 2002

Metal-ferroelectric-semiconductor(MFS) capacitors by using rapid thermal annealed $LiNbO_3$/Si structures were successfully fabricated and demonstrated nonvolatile memory operations of the MFS capacitors. The C-V characteristics of MFS capacitors showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3$thin film. The dielectric constant of the $LiNbO_3$film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 25. The gate leakage current density of MFS capacitor using a platinum electrode showed the least value of $1{\times}10^{-8}\textrm{A/cm}^2$ order at the electric field of 500 kV/cm. The minimum interface trap density around midgap was estimated to be about $10^{11}/cm^2$.eV. The typical measured remnant polarization(2Pr) value was about 1.2 $\mu\textrm{C/cm}^2$, in an applied electric field of $\pm$ 300 kv/cm. The ferroelectric capacitors showed no polarization degradation up to about $10^{10}$ switching cycles when subjected to symmetric bipolar voltage pulse in the 500 kHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.2
• /
• pp.321-327
• /
• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.6
• /
• pp.558-569
• /
• 2017

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.