• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Korean Journal of Construction Engineering and Management
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• v.11 no.3
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• pp.43-54
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• 2010

As Urban Regeneration is being carried out, stakeholders are most likely to have disagreements on their interests. Besides, dispersion of numerous communication routes and obscure decision processes aggravate the situation. Eventually, fragmented decision-making processes and complex structure lead to inefficient outcome and delay of projects. This paper is a study on decision-making support not only helps the program manager have more efficient and optimum decision, but also provides alternatives for Urban Regeneration. This study is conducted as follows. Firstly, the project process and the decision-making structure among stakeholders in Urban Regeneration are analyzed, and then the current status of decision-making in Urban Regeneration project is classified. Secondly, with literature study on "Gateway Review", the decision-making gateway review process in Urban Regeneration is defined, and then the "Gateway Review Elements" are listed. Thirdly, to establish gateway review process, this paper presents a check points, namely gate which supports a program manager to monitor and to control the program management in Urban Regeneration. Each gate has several supporting tools such as diagram of critical decision points relation, scheme of stakeholder, checklist. Fourthly, the proposed concept is verified by experts who have been carefully selected to provide their respective reviews. Finally, decision-making support gateway review system is modified based on their critiques and suggestions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.63-72
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• 2012

In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.65-75
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• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Elastomers and Composites
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• v.42 no.4
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• pp.209-216
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• 2007

Fatigue life prediction methodology of the rubber component made of vulcanized natural rubber under variable amplitude loadings was studied. The displacement-controlled fatigue tests were conducted at different levels and the maximum Green-Lagrange strain was selected as damage parameters. A fatigue life curve of the rubber represented by the maximum Green-Lagrange strain was determined from the nonlinear finite element analysis. The transmission load history of SAE as variable amplitude loading was used to perform the fatigue life prediction. And then a signal processing of variable loading by racetrack and simplified rainflow cycle counting methods were performed. The modified miner's rule as cumulative damage summation was used. Finally, when the gate value is 30%, the predicted fatigue life of the rubber component agreed well with the experimental fatigue lives with a factor of two.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.681-687
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• 2014

Nuclear industries have faced unfavorable circumstances such as an obsolescence of the instrumentation and control system, and therefore nuclear society is striving to resolve this issue fundamentally. IEC and IAEA judge that FPGA technology is a good replacement for Programmable Logic Controller (PLC) of Nuclear Instrumentation and Control System. FPGAs are currently highlighted as an alternative means for obsolete control systems. Because the main function inside an FPGA is initially developed as software, good software quality can impact the reliability of an FPGA-based controller. Therefore, it is necessary to establish a software development aspect strategy that enhances the reliability of an FPGA-based controller. In terms of software development, HDL-Programmed Device (HPD) Development Life Cycle is applied into FPGA-based Controller. The burn-in test and environmental(temperature) test should be performed in order to apply into nuclear instrumentation and control system. Therefore it is ensured that the developed FPGA-based controller are normally operated for 352 hours and 92 hours in test chamber of Korea Institute of Machinery and Materials (KIMM).

• Advances in concrete construction
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• v.16 no.6
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• pp.303-316
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• 2023

Using industrial wastes and construction and demolition (C&D) wastes is potentially advantageous for concrete production in terms of sustainability improvement. In this paper, a sustainable Self-Compacting Concrete (SCC) made with industrial wastes and C&D wastes was proposed by considerably replacing natural counterparts with recycled coarse aggregates (RCAs) and supplementary cementitious materials (SCMs) (i.e., Fly ash (FA), ground granulated blast furnace slag (GGBS) and silica fume (SF)). A total of 12 SCC mixes with various RCAs and different combination SCMs were prepared, which comprise binary, ternary and quaternary mixes. The mechanical properties in terms of compressive strength and static elasticity modulus of recycled aggregates (RA-SCC) mixes were determined and analyzed. Microstructural study was implemented to analyze the reason of improvement on mechanical properties. By means of life cycle assessment (LCA) method, the environmental impacts of RA-SCC with various RCAs and SCMs were quantified, analyzed and compared in the system boundary of "cradle-to-gate". In addition, the comparison of LCA results with respect to mechanical properties was conducted. The results demonstrate that the addition of proposed combination SCMs leads to significant improvement in mechanical properties of quaternary RA-SCC mixes with FA, GGBS and SF. Furthermore, quaternary RA-SCC mixes emit lowest environmental burdens without compromising mechanical properties. Thus, using the combination of FA, GGBS and SF as cement substitution to manufacture RA-SCC significantly improves the sustainability of SCC by minimizing the depletion of cement and non-renewable natural resources.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4392-4397
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• 2012

In this study, we used the commercial package (Unigraphics) to construct a junction box cable car when laser plastic parts have been processed using urethane resin(TSR-755) as a starting mold material. After construction, we carried out the filing, packing, cooling, and deforming analyzation using Injection Molding Analysis (Simpoe-Mold) to determine the gate positioning and automatic cooling cycle through the examination. The results show that inserting into the injection mold after processing ceramic has reduced the time of thermal conductivity of molding and cooling; and quick selection of gates and cooling lines could possibly cause an improvement of productivity.