• Journal of the Korean Magnetics Society
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• v.16 no.3
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• pp.182-185
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• 2006

In this work, we have constructed 3-axis flux-gate magnetometer for the attitude control of satellite. The constructed magnetometer shows uncertainty of ${\pm}1%$, noise level of $0.2nT/\sqrt{Hz}$ at 1 Hz under 1W power consumption. Environment test for satellite component, acceleration test and thermal cycle test were carried out. For the acceleration test, magnetometer was vibrated frequency ranging from 10 Hz to 1 kHz at 15 g (g : gravitational acceleration at earth), and for thermal cycle test, 4 times of thermal cycle were carried out temperature ranging from $-55^{\circ}C\;to\;+80^{\circ}C$ under vacuum of $1x10^{-6}Torr$.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.139-144
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• 2013

Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gate-level circuit aging analysis framework.

• Journal of The Korean Society of Agricultural Engineers
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• v.56 no.5
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• pp.67-75
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• 2014

In this study, the large-scale hydraulic model test was performed to investigate the hydraulic characteristics for development of the non-power soil cleaning and keeping system at the dike gate. The outlet height, outflow number, outflow discharge, and outflow cycle were compared and analyzed. The non-power soil cleaning and keeping system was most effective at 11.2 mm in the outlet height. And then the mean outflow cycle was 1.09 sec, and the mean outflow discharge was $0.00164m^3/s$. The total outflow number increased gradually as the water level of a water tank increased, and the outlet height decreased. As a level of water tank decreased, the mean outflow cycle was lengthened, and the unit outflow discharge increased. This result showed this system was most effective. To remove the silty clay deposited in facilities, the methods of excavation, dredging, high pressure washing, etc have been applied to the tidal facilities such as land reclamation, a small size fishing port, and a harbor for maintenance. However, this is extremely cost-ineffective, whereas the non-power soil cleaning and keeping system will bring about an enormously positive economic effect. In addition, when the non-power soil cleaning and keeping system is applied to the dike gate of land reclamation, a thorough examination of the local tidal data and the careful system planning are required to prevent the disaster damage caused by flooding.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.172-175
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• 2005

a-Si TFT는 TFT-LCD의 화소 스위칭(swiching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압의 이동이다. 펄스(pulse)형태로 인가되는 gate 전압에 의한 문턱 전압 이동은 a-Si:H gate에 인가되는 펄스의 크기, duty cycle, drain pulse의 크기 및 동작 온도에 기인하며 실험결과를 통해 입증된다. 초기의 DC Stress 측정 Data를 이용하여 문턱전압이동을 모델링/시뮬레이션한 결과 a-Si:H gate 회로설계 및 펄스 조건에 따라 stress시간에 따른 gate의 출력 파형 예측이 가능하고 상온에서 Von=21V를 인가한 결과, 약 4년후에서 시프트레지스터 출력 파형이 열화되기 시작한다.

• Proceedings of the Korean Reliability Society Conference
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• 2001.06a
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• pp.91-97
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• 2001

These Study are for the development of the reliability assessment test code and test equipment and test procedures of the heavy sluice gate hydraulic cylinder. Because there is no reliability test code for the heavy sluice gate hydraulic cylinder inside and outside of the country, the modified reliability test code is made reference for the related existing standards like as ISO, JIS, MIL, TUV, DIN, KS and etc. In this study, the novel method is proposed to evaluate efficiency of the heavy sluice gate hydraulic cylinder on the loading conditions and established the conditions of the acceleration life test to reduce the testing time and cycles. The testing equipments for life test, lode operating test, high and low temperature test and salt spray test have been established for 8 month, and the reliability tests are accomplished. The test results of the heavy sluice gate hydraulic cylinder which is produced and tested initially in Korea are satisfied the durability life cycle on the using conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• Journal of The Korean Society of Agricultural Engineers
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• v.53 no.3
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• pp.59-64
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• 2011

The objective of the study is to develop life cycle inventory (LCI) database of dam, a major facility for irrigation water supply. The types of database developed are three out of nine dams according to the size of the wate r storage capacity: two kinds larger than 500,000 $m^3$ depending on gate for discharging (Type 1) and the other dam smaller than 500,000 $m^3$ (Type 2). According to the LCI analysis, type 1 larger than 500,000 $m^3$ storage capacity with gate has the lowest environment impact in the 6 impact categories. The impact of the type 1 accounts for 7~35 % of the type 2 for supplying irrigation water. Comparing with the environment impacts of water for other uses such as drinking and industrial water, the impacts of 1 $m^3$ irrigation water supply is 4~45 % of the one for industrial water supply and 1~16 % of the drinking water's. The three types of LCI DB on the irrigation water by dams will be useful in the application of Life Cycle Assessment in agricultural products and environmental labelling including carbon footprint since it is complied to the guidelines of LCI DB constr uction issued by Ministry of Environment and Ministry of Knowledge Economy.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.50-53
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• 2001

In this study, gate leakage current mechanism has been analyzed for GaAs MESFET with different temperatures ranging from 27$^{\circ}C$ to 300$^{\circ}C$ . It is expected that the thermionic and field emission at the MS contact will dominate the current flow. Thermal cycle is applied to test the reliability of the device. From the results, it is proved that thermal stress gradually increases the gate leakage current at the same bias conditions and leads to the breakdown and failure mechanism which is critical in the field equipment. Finally the gate contact under the repeated thermal shock has been tested to check the quality of Schottky barrier and the current will be expressed in the analytical from to associate with the electrical characteristics of the device.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.577-595
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• 2017

${\bullet}$ Silicon Carbide (SiC) had excellent material properties as the base material for next generation of power semiconductor. In developing SiC MOSFET, gate oxide reliability issues had to be first overcome before commercial application. Besides, a high and stable gate-source voltage threshold $V_{GS(th)}$ is also an important parameter for operation robustness. SiC MOSFET with such characteristics can directly use existing high-speed IGBT gate driver IC's. ${\bullet}$ The linear voltage drop characteristics of SiC MOSFET will bring lower conduction loss averaged over full AC cycle compared to similarly rate IGBT. Lower switching loss enable higher switching frequency. Using package with auxiliary source terminal for gate driving will further reduce switching losses. Dynamic characteristics can fully controlled by simple gate resistors. ${\bullet}$ The low switching losses characteristics of SiC MOSFET can substantially reduce power losses in high switching frequency operation. Significant power loss reduction is also possible even at low switching frequency and low switching speed. in T-type 3-level topology, SiC MOSFET solution enable three times higher switching freqeuncy at same efficiency.