• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.598-599
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• 2017

In motor application, High efficiency is important. So Design engineer select small gate resistor for lower switching. But There is side effect with small gate resistor. It makes large dv/dt and system request large EMI filter. It makes price increase. This paper introduce about gate drive IC which have solution both of lower loss and EMI issue.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.542-545
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• 2002

This paper deals with the optimization inverter design and minimization Conduced EMI noise by customizing IPM(Intelligent Power Module). Generally, In case of IPM, we realized that the trade-off relation between switching loss and spike voltage. Higher gate resistor causes tile lower spike voltage and the higher turn-off switching loss. But we know that the life cycle of inverter and the susceptibility of noise, so we optimized the gate resistor. Proposed method is that optimized the gate resistor suitable for the inverter and motor. The simulation and experimental results show that the spike voltage and Conduced EMI noise can be reduced without the additional circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 전력전자학회논문지
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• 제4권2호
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• pp.111-121
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• 1999

대용량 IGBT를 위한 새로운 능동 게이트 구동회로를 제안한다. IGBT의 우수한 스위칭 성능을 성취하기 위해 필요한 여러 구동 조건들을 최적으로 조합시킨 게이트 구동 회로이다. 스위칭 노이즈와 스트레스를 감소시키기 위해 필요한 느린 구동 조건과 스위칭 속도를 증가시키고 손실을 저감시키기 위해 요구되는 고속 구동 조건들을 동시에 만족시키고 있다. 또한 작은 전류의 턴-온시 발생되는 진동현상을 효과적으로 감쇠시킬 수 있는 특성을 지니고 있다.

• 전력전자학회논문지
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• 제8권4호
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• pp.313-320
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• 2003

본 논문에서는 부가적인 회로의 추가 없이 IPM 내부 IGBT의 게이트 저항을 시스템에 최적화된 값으로 선정하여 dv/dt 및 di/dt를 감소시키고 이로 인한 전도 EMI 노이즈를 저감하여 엘리베이터 시스템에 최적화된 전련변환장치를 설계한다. 주문형 IPM을 엘리베이터용 인버터 시스템에 최적화하기 위하여 시스템에 적용될 전력변환장치의 게이트 저항에 따른 Spike 전압 및 전동기 서지전압, 스위칭 손실에 따른 IPM 케이스와 방열판의 온도 변화등을 시뮬레이션 및 계측한다. 결과적으로 IPM의 게이트 저항을 시스템에서 요구하는 수명에 따라 최적화하여 전도되는 EMI 노이즈가 특정 주파수 대역에서 약 5∼10 [dB$\mu$Vl 저감됨을 확인할 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.325-328
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• 2002

In this paper. we propose a floating resistor with positive and negative resistance operating at lower supply voltages. The circuit uses only two transistors between the supply voltages. which enable to operate it at low supply voltages. Moreover. the circuit uses fewer number of transistors compared to the reported work. The gate terminal is used in this circuit for the current addition/subraction at the terminals of resistor. The characteristic of the proposed circuit is verified using HSPICE for the power supply +/-1.5V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.759-762
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• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• 대한전자공학회논문지
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• 제11권2호
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• pp.40-45
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• 1974

SCR에서도 anode 전류가 미소(약수 10mA∼수100mA이내)할때에는 게이트 전fur을 조정하므로써 anode전류를 조절할수 있다. 이를 이용하여 cathode 각로에 적당치의 저항을 삽입하여 게이트 회로에 부성저항특성을 나타내게 할 수 있고 간단한 정형파 발진회로를 만들었다.

• Journal of Power Electronics
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• 제15권5호
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• pp.1402-1408
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• 2015

A MOSFET's gate driver based on magnetic coupling is investigated. The gate driver can meet the demands in applications for wide range of duty cycles and high frequency. Fully galvanic isolation can be realized, and no auxiliary supply is needed. The driver is insensitive to the leakage inductor of the isolated transformer. No gate resistor is needed to damp the oscillation, and thus the peak output current of the gate driver can be improved. Design of the driving transformer can also be made more flexible, which helps to improve the isolation voltage between the power stage and the control electronics, and aids to enhance the electromagnetic compatibility. The driver's operation principle is analyzed, and the design method for its key parameters is presented. The performance analysis is validated via experiment. The disadvantages of the traditional magnetic coupling and optical coupling have been conquered through the investigated circuit.

• 한국광학회:학술대회논문집
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• 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.